Matches 1 - 29 out of 29
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7425491 Nanowire transistor with surrounding gate  
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a...
7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7410910 Lanthanum aluminum oxynitride dielectric films  
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum...
7405454 Electronic apparatus with deposited dielectric layers  
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using...
7374964 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics  
The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to...
7371627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7368365 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7368344 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7323380 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7298638 Operating an electronic device having a vertical gain cell that includes vertical MOS transistors  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7285812 Vertical transistors  
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
7259434 Highly reliable amorphous high-k gate oxide ZrO2  
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO 2 gate oxides are provided. Also shown is a gate...
7247570 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7241658 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7241654 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7229895 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7224024 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7199417 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
7151690 6F2 3-Transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
7149109 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7081421 Lanthanide oxide dielectric layer  
A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic...
6975531 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6956256 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
6943083 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6940761 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6934209 Temperature compensated T-RAM memory device and method  
A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the...
6838723 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS bipolar capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6804142 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6781907 Temperature compensated T-RAM memory device and method  
A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the...
Matches 1 - 29 out of 29