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7370306 |
Method and apparatus for designing a pattern on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
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7353490 |
Power network synthesizer for an integrated circuit design
A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard...
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7346869 |
Power network analyzer for an integrated circuit design
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another,...
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7290242 |
Pattern generation on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
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7281227 |
Method and device for the computer-aided design of a supply network
A supply network is designed for a microelectronic circuit by a method for computer-aided design, in that an outline of the microelectronic circuit is detected and the supply network is generated...
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7266789 |
Method and apparatus of optimizing the IO collar of a peripheral image
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of...
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7203916 |
System, method and program product for positioning I/O pads on a chip
Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit...
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7174524 |
Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring
A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated...
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7100136 |
LSI design system
Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart...
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7065728 |
Method for placing electrostatic discharge clamps within integrated circuit devices
A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible...
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7062740 |
System and method for reducing design cycle time for designing input/output cells
A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be...
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6934928 |
Method and apparatus for designing a pattern on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
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6898779 |
Pattern generation on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
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6701509 |
Integrated circuit power and ground routing
An integrated circuit includes a plurality of blocks of cells, and a plurality of layers with conductors for signal and power routing. Power and ground connections for individual cells are supplied...
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6668356 |
Method for designing circuits with sections having different supply voltages
In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being allocated a supply voltage. The...
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6591410 |
Six-to-one signal/power ratio bump and trace pattern for flip chip design
A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein...
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6576147 |
Method of layout compaction
It is an object of the invention to carry out layout compaction in which optical proximity effect is taken account of the irregularly disposed layout patterns also contained within circuit design...
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