Matches 1 - 15 out of 15
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7429536 Methods for forming arrays of small, closely spaced features  
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with...
7413981 Pitch doubled circuit layout  
In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first...
7396781 Method and apparatus for adjusting feature size and position  
Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are...
7393789 Protective coating for planarization  
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed,...
7390746 Multiple deposition for integration of spacers in pitch multiplication process  
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer...
7368362 Methods for increasing photo alignment margins  
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines...
7361569 Methods for increasing photo-alignment margins  
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines...
7287325 Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing  
Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The...
7268054 Methods for increasing photo-alignment margins  
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines...
7253118 Pitch reduced patterns relative to photolithography features  
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form...
7084454 Nonvolatile integrated semiconductor memory  
A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores...
7026170 Methods of controlling optical properties of a capping insulating layer on memory devices, and system for performing same  
The present invention is generally directed to various methods of controlling optical properties of a capping insulating layer on memory devices, and system for performing same. The method includes...
6808986 Method of forming nanocrystals in a memory device  
Nanocrystals ( 22 ) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric ( 18 ) overlies a substrate ( 12 ) and is placed in a chemical vapor...
6784103 Method of formation of nanocrystals on a semiconductor structure  
Nanocrystals ( 22 ) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric ( 18 ) overlies a substrate ( 12 ) and is placed in a chemical vapor...
6762454 Stacked polysilicon layer for boron penetration inhibition  
A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed...
Matches 1 - 15 out of 15