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7432122 Electronic device and a process for forming the electronic device  
An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the...
7425491 Nanowire transistor with surrounding gate  
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a...
7416943 Peripheral gate stacks and recessed array gates  
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices...
7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7371627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7368365 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7368344 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7336105 Dual gate transistor keeper dynamic logic  
A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The...
7285812 Vertical transistors  
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
7247570 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7229895 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7192876 Transistor with independent gate structures  
A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one...
7183164 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7120046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines  
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward...
7098502 Transistor having three electrically isolated electrodes and method of formation  
A transistor ( 10 ) is formed having three separately controllable gates ( 44, 42, 18 ). The three gate regions may be electrically biased differently and the gate regions may have different...
7018876 Transistor with vertical dielectric structure  
A transistor ( 103 ) with a vertical structure ( 113 ) that includes a dielectric structure ( 201 ) below a semiconductor structure ( 109 ). The semiconductor structure includes a channel region (...
6969656 Method and circuit for multiplying signals with a transistor having more than one independent gate structure  
A double gate semiconductor device ( 2006 ) is used beneficially as a multiplier ( 2000 ). The double gate semiconductor device ( 2006 ) has a lateral fin ( 105 ) as the channel region with the...
6967143 Semiconductor fabrication process with asymmetrical conductive spacers  
A semiconductor process and resulting transistor includes forming conductive extension spacers ( 146, 150 ) on either side of a gate electrode ( 116 ). Conductive extensions ( 146, 150 ) and gate...
6903967 Memory with charge storage locations and adjacent gate structures  
A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the...
6831310 Integrated circuit having multiple memory types and method of formation  
A transistor ( 10 ) is formed having three separately controllable gates ( 44, 42, 18 ). The three gate regions may be electrically biased differently and the gate regions may have different...
Matches 1 - 20 out of 20