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7369434 |
Flash memory with multi-bit read
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic...
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7353313 |
General input/output architecture, protocol and related methods to manage data integrity
An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g.,...
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7231486 |
General input/output architecture, protocol and related methods to support legacy interrupts
An enhanced general input/output communication architecture, protocol and related methods are presented.
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7177971 |
General input/output architecture, protocol and related methods to provide isochronous channels
An enhanced general input/output communication architecture, protocol and related methods are presented.
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7152128 |
General input/output architecture, protocol and related methods to manage data integrity
An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general...
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7127574 |
Method and apparatus for out of order memory scheduling
Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a...
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7127573 |
Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions
A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication...
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6970978 |
System and method for providing a pre-fetch memory controller
A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a...
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6654860 |
Method and apparatus for removing speculative memory accesses from a memory access queue for issuance to memory or discarding
A memory controller generates speculative and non-speculative memory access requests. Several approaches are used to prevent speculative memory access requests from interfering with non-speculative...
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6504549 |
Apparatus to arbitrate among clients requesting memory access in a video system and method thereof
A method and apparatus dealing with optimizing the arbitration between clients requesting data. In particular, a set of rules determining which client request will provide an optimized subsequent...
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