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7425491 Nanowire transistor with surrounding gate  
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a...
7416943 Peripheral gate stacks and recessed array gates  
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices...
7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7405444 Micro-mechanically strained semiconductor film  
A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local...
7394111 Strained Si/SiGe structures by ion implantation  
One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon...
7391072 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7372097 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7372096 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7371627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7369436 Vertical NAND flash memory device  
Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
7368365 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7368344 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7339239 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7332773 Vertical device 4F2 EEPROM memory  
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
7326597 Gettering using voids formed by surface transformation  
One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in...
7285812 Vertical transistors  
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
7282762 4F2 EEPROM NROM memory arrays with vertical devices  
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
7274067 Service programmable logic arrays with low tunnel barrier interpoly insulators  
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a...
7273788 Ultra-thin semiconductors bonded on glass substrates  
A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer...
7271445 Ultra-thin semiconductors bonded on glass substrates  
A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer...
7271065 Horizontal memory devices with vertical gates  
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity...
7262428 Strained Si/SiGe/SOI islands and processes of making same  
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under...
7260125 Method of forming mirrors by surface transformation of empty spaces in solid state materials  
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by...
7247570 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7241654 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7229895 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7202530 Micro-mechanically strained semiconductor film  
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate...
7198974 Micro-mechanically strained semiconductor film  
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate...
7187587 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators  
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address...
7183164 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7166886 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators  
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second...
7164294 Method for forming programmable logic arrays using vertical gate transistors  
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each...
7164188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials  
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the...
7157771 Vertical device 4F2 EEPROM memory  
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
7153753 Strained Si/SiGe/SOI islands and processes of making same  
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under...
7151030 Horizontal memory devices with vertical gates  
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity...
7148538 Vertical NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
7142577 Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon  
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by...
7136302 Integrated circuit memory device and method  
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region...
7132711 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7126183 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers  
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type...
7120046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines  
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward...
7115480 Micromechanical strained semiconductor by wafer bonding  
One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first...
7112841 Graded composition metal oxide tunnel barrier interpoly insulators  
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type...
7095075 Apparatus and method for split transistor memory having improved endurance  
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device...
7087954 In service programmable logic arrays with low tunnel barrier interpoly insulators  
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a...
7075829 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators  
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address...
7075146 4F2 EEPROM NROM memory arrays with vertical devices  
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
7074673 Service programmable logic arrays with low tunnel barrier interpoly insulators  
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a...
7068544 Flash memory with low tunnel barrier interpoly insulators  
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region...
Matches 1 - 50 out of 75 1 2 >