Matches 1 - 18 out of 18
Match Document Document Title
7398413 Memory device signaling system and method with independent timing calibration for parallel signal paths  
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory...
7378891 Measure-controlled circuit with frequency control  
Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal...
7346099 Network fabric physical layer  
A network fabric physical layer includes a driver coupled to a receiver via a bus, which implements a multiphase encoded protocol. A multiphase sequencer sequences (data or command/control) words...
7319728 Delay locked loop with frequency control  
A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals...
7299329 Dual edge command in DRAM  
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of...
7212057 Measure-controlled circuit with frequency control  
A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based...
7139345 Method and circuit for adjusting the timing of output data based on the current and future states of the output data  
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to...
7103126 Method and circuit for adjusting the timing of output data based on the current and future states of the output data  
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to...
6996632 Multiphase encoded protocol and synchronization of buses  
A multiphase encoded protocol has sufficient density of commands to allow a rich language to be realized on a bus. When ten field bits are dedicated to commands, it is possible to have more than...
6956415 Modular DLL architecture for generating multiple timings  
A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with...
6920540 Timing calibration apparatus and method for a memory device signaling system  
A memory system includes a memory controller and a memory component coupled to each other. An interface of the memory component is configured to receive a first signal from the memory controller...
6915399 Cross-clock domain data transfer method and apparatus  
An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a...
6839290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe  
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate...
6801070 Measure-controlled circuit with frequency control  
A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based...
6789209 Semiconductor integrated circuit device  
In a semiconductor integrated circuit device operating in synchronism with a clock supplied from the outside of the device, there is provided a circuit generating, from the clock, an output strobe...
6756925 PSK RSFQ output interface  
A Rapid Single-Flux-Quantum (“RSFQ”) encoder output interface device is provided. The RSFQ output interface device includes a variable phase multi-junction voltage controlled oscillator (VCO)...
6621760 Method, apparatus, and system for high speed data transfer using source synchronous data strobe  
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate...
5315851 Steering lock device for vehicle  
In a steering lock device used for a vehicle in which the locking member allows a steering shaft to rotate when an inner cylinder of a cylinder lock moves to ON position by the operation of a key,...
Matches 1 - 18 out of 18