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7027349 Method for selecting memory device in response to bank selection signal  
A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection...
6920591 Measuring an error rate in a communication link  
An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate...
6850107 Variable delay circuit and method, and delay locked loop, memory device and computer system using same  
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input...
6842393 Method for selecting one or a bank of memory devices  
A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection...
6759883 Variable delay circuit and method, and delay locked loop, memory device and computer system using same  
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input...
6735148 Variable delay circuit and method, and delay locked loop, memory device and computer system using same  
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input...
6727734 Variable delay circuit and method, and delay locked loop, memory device and computer system using same  
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input...
6671845 Packet-based device test system  
A packet generator that increases the output speed of column and row addresses and data provided by a semiconductor device test system. The packet generator receives column and row addresses and...
6564162 Method and apparatus for improving electrical verification throughput via comparison of operating-point differentiated test results  
The operating-point differentiated test results are obtained by running a code sequence on the device at a first operating point to generate predicted results and then running the same code...
6535450 Method for selecting one or a bank of memory devices  
A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection...
Matches 1 - 10 out of 10