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7400525 Memory cell with independent-gate controlled access devices and memory using the cell  
A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a...
7362617 Nonvolatile semiconductor memory device and method of rewriting data thereof  
The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between...
7333370 Method to prevent bit line capacitive coupling  
Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate,...
7326992 Nonvolatile memory cell with multiple floating gates formed after the select gate  
In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 )...
7301196 Nonvolatile memories and methods of fabrication  
In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then...
7294883 Nonvolatile memory cells with buried channel transistors  
In a nonvolatile memory cell ( 110 ), the select gate transistor is formed as a buried channel transistor to increase the transistor current.
7274063 Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions  
In a nonvolatile memory cell having at least two floating gates, each floating gate ( 160 ) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select...
7230295 Nonvolatile memory cell with multiple floating gates formed after the select gate  
In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 )...
7214585 Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges  
A widened contact area ( 170 X) of a conductive feature ( 170 ) is formed by means of self-alignment between an edge ( 170 E 2 ) of the conductive feature and an edge ( 140 E) of another feature (...
7195964 Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit  
A gate dielectric ( 150 ) for a gate ( 160 ) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate ( 140 ). The dielectric thickness on the other gate is...
7190019 Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges  
A widened contact area ( 170 X) of a conductive feature ( 170 ) is formed by means of self-alignment between an edge ( 170 E 2 ) of the conductive feature and an edge ( 140 E) of another feature (...
7169667 Nonvolatile memory cell with multiple floating gates formed after the select gate  
In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 )...
7101757 Nonvolatile memory cells with buried channel transistors  
In a nonvolatile memory cell ( 110 ), the select gate transistor is formed as a buried channel transistor to increase the transistor current.
7060565 Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates  
A memory cell ( 110 ) has a select gate ( 140 ) and at least two floating gates ( 160 ). A gate dielectric ( 150 ) for the floating gates ( 160 ) is formed by thermal oxidation simultaneously with...
7057231 Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate  
A floating gate ( 110 ) of a nonvolatile memory cell is formed in a trench ( 114 ) in a semiconductor substrate ( 220 ). A dielectric ( 128 ) covers the surface of the trench. The wordline ( 140 )...
7053438 Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates  
In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 )...
7052947 Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates  
In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 )...
7045854 Non-volatile semiconductor memory  
An object of the present invention is to provide a semiconductor memory device suitable for larger-capacity storage because of its ability to store 3 or more bits in one element and capable of a...
7018895 Nonvolatile memory cell with multiple floating gates formed after the select gate  
In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 )...
7005338 Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate  
A floating gate ( 110 ) of a nonvolatile memory cell is formed in a trench ( 114 ) in a semiconductor substrate ( 220 ). A dielectric ( 128 ) covers the surface of the trench. The wordline ( 140 )...
6995060 Fabrication of integrated circuit elements in structures with protruding features  
A structure is obtained having a semiconductor substrate, the structure having an upward protruding feature ( 140 ). A first layer ( 160 ) is formed on the structure. The first layer ( 160 ) has a...
6977869 Non-volatile memory and method of operation  
A method of programming and erasing an electrically erasable programmable read-only memory (EEPROM)device includes performing a band-to-band tunneling induced hot-electrons program and performing a...
6974739 Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit  
A gate dielectric ( 150 ) for a gate ( 160 ) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate ( 140 ). The dielectric thickness on the other gate is...
6962852 Nonvolatile memories and methods of fabrication  
To fabricate a nonvolatile memory, a select gate ( 140 ) is formed over a semiconductor substrate. A dielectric ( 810, 1010, 1030 ) is formed over the select gate. A floating gate layer ( 160 ),...
6962851 Nonvolatile memories and methods of fabrication  
In a nonvolatile memory, substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions are dielectric regions protruding above the substrate....
6951782 Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions  
In a nonvolatile memory cell having at least two floating gates, each floating gate ( 160 ) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select...
6930348 Dual bit split gate flash memory  
The dual bit split gate flash memory of the invention comprises a plurality of memory cells wherein each memory cell comprises a select gate overlying a substrate and isolated from the substrate by...
6919607 Structure of two-bit mask read-only memory device and fabricating method thereof  
A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a...
6902974 Fabrication of conductive gates for nonvolatile memories from layers with protruding portions  
A control gate layer ( 170 ) for a nonvolatile memory cell is formed over a select gate ( 140 ). The control gate layer protrudes upward over the select gate. An auxiliary layer (1710) is formed...
6894915 Method to prevent bit line capacitive coupling  
Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate,...
6885044 Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates  
In a nonvolatile memory array in which each cell ( 110 ) has two floating gates ( 160 ), for any two consecutive memory cells, one source/drain region ( 174 ) of one of the cells and one...
6846712 Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates  
In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 ) for these peripheral transistors and the gate...
6844586 Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates  
In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 ) for these peripheral transistors and the gate...
6744664 Dual-bit floating-gate flash cell structure and its contactless flash memory arrays  
A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being...
6704222 Multi-state operation of dual floating gate array  
Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably...
6587381 Programming method for non-volatile semiconductor memory device  
A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL 1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to...
6480414 Multi-level memory cell  
A multi-level memory cell has a substrate, a first floating gate, a second floating gate and a control gate. A first doped region, a second doped region and a channel region located between the...
Matches 1 - 37 out of 37