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7362646 Semiconductor memory device  
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the...
7362641 Method and system for low power refresh of dynamic random access memories  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
7359271 Gate induced drain leakage current reduction by voltage regulation of master wordline  
A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated...
7275130 Method and system for dynamically operating memory in a power-saving error correcting mode  
A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to...
7158357 Capacitor design in ESD circuits for eliminating current leakage  
An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) is disclosed. The ESD protection circuit has a RC module having a resistor and capacitor connected in series; and...
7072237 Method and system for low power refresh of dynamic random access memories  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
6965540 Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode  
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode...
6925021 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs  
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower...
6850457 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS  
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower...
6839300 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs  
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower...
6838331 Method and system for dynamically operating memory in a power-saving error correction mode  
A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to...
6826074 Semiconductor memory device  
In a semiconductor memory device, a precharge potential for non-selected bit lines among a plurality of bit lines, supplied by a HPR voltage source, is set at a value (for example, ½ Vcc=0.4 V)...
6751159 Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode  
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode...
6751143 Method and system for low power refresh of dynamic random access memories  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
6731564 Method and system for power conservation in memory devices  
According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a...
6504745 High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines  
A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell...
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