Matches 1 - 34 out of 34
Match Document Document Title
7398413 Memory device signaling system and method with independent timing calibration for parallel signal paths  
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7193910 Adjustable timing circuit of an integrated circuit  
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay...
7168027 Dynamic synchronization of data capture on an optical or other high speed communications link  
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver....
7159092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
7130227 Adjustable timing circuit of an integrated circuit  
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7016451 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6959016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges  
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with...
6954097 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6920540 Timing calibration apparatus and method for a memory device signaling system  
A memory system includes a memory controller and a memory component coupled to each other. An interface of the memory component is configured to receive a first signal from the memory controller...
6912680 Memory system with dynamic timing correction  
A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the...
6812753 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal  
A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled...
6801989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
6759882 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal  
A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled...
6662304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a...
6647523 Method for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the...
6643789 Computer system having memory device with adjustable data clocking using pass gates  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6618283 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal  
A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled...
6611475 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal  
A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled...
6593786 Register controlled DLL reducing current consumption  
A delay locked loop (DLL) usable in a semiconductor memory device and capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode,...
EP1300265A1 Vehicle rear suspension apparatus  
A vehicle suspension apparatus includes an axle which comprises a pair of trailing arms and a transverse beam (12). Resilient bushings connect the forward ends of the trailing arms to the vehicle...
6526106 Synchronous circuit controller for controlling data transmission between asynchrous circuit  
A synchronous circuit controller includes a delay section for delaying data with a predetermined amount of delay, and outputting corresponding delay data, a latch section for latching each of the...
6499111 Apparatus for adjusting delay of a clock signal relative to a data signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6490224 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6490207 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6483757 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6477675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
6470060 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6445330 Capacitively coupled references for isolated analog-to-digital converter systems  
The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation...
6179328 Vehicle rear suspension apparatus  
A vehicle suspension apparatus includes an axle. The axle includes a pair of trailing arms with a transverse beam. Resilient bushings connect the forward ends of the trailing arms to the vehicle...
EP0872367A2 Vehicle rear suspension apparatus  
A vehicle suspension apparatus includes an axle (10) which comprises a pair of trailing arms (14) and a transverse beam (12). Resilient bushings (38) connect the forward ends of the trailing arms...
Matches 1 - 34 out of 34