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7424561 |
Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured...
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7394823 |
System having configurable interfaces for flexible system configurations
An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of...
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7369447 |
Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously...
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7266587 |
System having interfaces, switch, and memory bridge for CC-NUMA operation
A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain...
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7206879 |
Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured...
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7123521 |
Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously...
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7003631 |
System having address-based intranode coherency and data-based internode coherency
A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is...
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6993631 |
L2 cache maintaining local ownership of remote coherency blocks
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first...
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6965973 |
Remote line directory which covers subset of shareable CC-NUMA memory space
A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total...
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6941406 |
System having interfaces and switch that separates coherent and packet traffic
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the...
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6748479 |
System having interfaces and switch that separates coherent and packet traffic
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the...
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EP1363192A1 |
Level 2 cache with local ownership of coherency blocks
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first...
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6493798 |
Upgradeable cache circuit using high speed multiplexer
An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache)...
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