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7423463 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
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7423462 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
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7414444 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
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7368965 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
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7276946 |
Measure-controlled delay circuits with reduced phase error
Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample...
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7095261 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
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6822922 |
Clock synchronous circuit
For a reset operation of a state-holding section after monitoring a delay time necessary for synchronizing an external clock with an internal clock, a state-holding unit of an n-th stage is reset,...
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6806753 |
Delay circuit and synchronous delay apparatus
A delay circuit, including a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second...
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6711092 |
Semiconductor memory with multiple timing loops
A semiconductor memory with multiple timing loops for optimizing memory access operations. A clock generator circuit is provided for generating an internal memory clock based on an external clock...
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6396322 |
Delay locked loop of a DDR SDRAM
A delay locked loop is disclosed which is capable of operating at both of a rising edge and a falling edge of a clock. The delay locked loop includes: a first differential amplifier receiving a...
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6323705 |
Double cycle lock approach in delay lock loop circuit
A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop circuitry which is designed so as to significantly reduce the locking period associated with achieving the lock...
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6292411 |
Delay control circuit synchronous with clock signal
A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward...
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6281728 |
Delay locked loop circuit
A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal; first oscillation means for generating a first pulse signal;...
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