Matches 1 - 46 out of 46
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EP1970439A2 Cell culture support and manufacture thereof  
An object of the present invention is to provide a cell culture support making the detachment of a cell sheet easy as well as enabling the formation of a uniform cell sheet. The present invention...
7425491 Nanowire transistor with surrounding gate  
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a...
7410867 Vertical transistor with horizontal gate layers  
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic...
7374990 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array  
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
7369436 Vertical NAND flash memory device  
Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
7339239 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7332773 Vertical device 4F2 EEPROM memory  
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
7323380 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7298638 Operating an electronic device having a vertical gain cell that includes vertical MOS transistors  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7282762 4F2 EEPROM NROM memory arrays with vertical devices  
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
7248988 System and method for reducing temperature variation during burn in  
Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated...
7242205 System and method for reducing heat dissipation during burn-in  
Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage...
7241658 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7241655 Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array  
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
7241654 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
EP1801199A1 CYTODETACHING AGENT AND METHOD OF DETACHING CELL SHEET  
A cell-sheet releasing agent of the present invention contains an aminated polyrotaxane. The polyrotaxane constituting the skeleton of the cell-releasing agent of the present invention has a...
7224024 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7199417 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
7157771 Vertical device 4F2 EEPROM memory  
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
7151690 6F2 3-Transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
7149109 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7148538 Vertical NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
7115939 Floating gate transistor with horizontal gate layers stacked next to vertical body  
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic...
7095075 Apparatus and method for split transistor memory having improved endurance  
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device...
7075146 4F2 EEPROM NROM memory arrays with vertical devices  
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
7015525 Folded bit line DRAM with vertical ultra thin body transistors  
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
6995057 Folded bit line DRAM with vertical ultra thin body transistors  
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
6975531 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6956256 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
6943083 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6940761 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6903367 Programmable memory address and decode circuits with vertical body transistors  
Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar...
6900650 System and method for controlling temperature during burn-in  
Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to...
6897671 System and method for reducing heat dissipation during burn-in  
Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage is...
6894532 Programmable logic arrays with ultra thin body transistors  
Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane...
6890812 Method of forming a memory having a vertical transistor  
Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar...
6881627 Flash memory with ultra thin vertical body transistors  
Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating...
6861708 Semiconductor memory device having a low potential body section  
This semiconductor device is provided with a wiring called a body line (BDL), a body section of a memory cell transistor is connected to this body line (BDL), and a potential of the body section is...
6838723 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS bipolar capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6804142 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6768144 Method and apparatus for reducing leakage current in an SRAM array  
A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first...
6744094 Floating gate transistor with horizontal gate layers stacked next to vertical body  
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic...
6638826 Power MOS device with buried gate  
An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain...
6515348 Semiconductor device with FET MESA structure and vertical contact electrodes  
A semiconductor device comprises one or more field effect devices (FD) having source and drain regions ( 5 and 6 ) spaced apart by a body region ( 3 a ). A gate structure ( 7 a , 7 b ),...
6445035 Power MOS device with buried gate and groove  
An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain...
6274453 Memory cell configuration and production process therefor  
A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a...
Matches 1 - 46 out of 46