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7434081 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7433441 System and method for adaptively deskewing parallel data signals relative to a clock  
A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data...
7428644 System and method for selective memory module power management  
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired...
7418526 Memory hub and method for providing memory sequencing hints  
A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of...
7418071 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
7415567 Memory hub bypass circuit and method  
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub...
7415404 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
7412574 System and method for arbitration of memory responses in a hub-based memory system  
A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers...
7412571 Memory arbitration system and method having an arbitration packet protocol  
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data...
7412566 Memory hub and access method having internal prefetch buffers  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory...
7411807 System and method for optically interconnecting memory devices  
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control...
7398413 Memory device signaling system and method with independent timing calibration for parallel signal paths  
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory...
7397725 Single-clock, strobeless signaling system  
A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing...
7392331 System and method for transmitting data packets in a computer system having a memory hub architecture  
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream...
7389364 Apparatus and method for direct memory access in a hub-based memory system  
A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one...
7386661 Power save module for storage controllers  
A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in...
7386649 Multiple processor system and method including multiple memory hub modules  
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and...
7382639 System and method for optically interconnecting memory devices  
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7370134 System and method for memory hub-based expansion bus  
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also...
7366920 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
System and method for selective memory module power management  
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired...
7363419 Method and system for terminating write commands in a hub-based memory system  
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub....
7353320 Memory hub and method for memory sequencing  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit...
7336435 Method and system for collecting servo field data from programmable devices in embedded disk controllers  
A servo controller for an embedded disk controller comprises a read channel interface that includes a programmable control logic that receives a servo field detected signal from a module that...
7330992 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7313715 Memory system having stub bus configuration  
A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both...
7310752 System and method for on-board timing margin testing of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7310748 Memory hub tester interface and method for use thereof  
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test...
7299329 Dual edge command in DRAM  
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of...
7289378 Reconstruction of signal timing in integrated circuits  
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface...
7289347 System and method for optically interconnecting memory devices  
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control...
7287102 System and method for concatenating data  
A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start...
7286441 Integrated memory controller  
A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory,...
7282947 Memory module and method having improved signal routing topology  
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches...
7278060 System and method for on-board diagnostics of memory modules  
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving...
7272682 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Memory hub bypass circuit and method  
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub...
7266633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules  
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least...
7260685 Memory hub and access method having internal prefetch buffers  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory...
7257683 Memory arbitration system and method having an arbitration packet protocol  
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data...
7254331 System and method for multiple bit optical data transmission in memory systems  
The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of light so that each pulse of optical...
7251714 Method and system for capturing and bypassing memory transactions in a hub-based memory system  
A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of...
7249236 Method and system for controlling memory accesses to memory modules having a memory hub architecture  
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding...
7245145 Memory module and method having improved signal routing topology  
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches...
7242213 Memory module and method having improved signal routing topology  
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches...
7240267 System and method for conducting BIST operations  
Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7231306 Method and apparatus for calibrating static timing offsets across multiple outputs  
Methods and apparatuses for calibrating out static timing offsets across multiple outputs of a transmitting device are provided. In accordance with at least one embodiment, a signal is selected as...
7222213 System and method for communicating the synchronization status of memory modules during initialization of the memory modules  
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least...
7222210 System and method for memory hub-based expansion bus  
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also...
7222197 Apparatus and method for direct memory access in a hub-based memory system  
A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one...
Matches 1 - 50 out of 156 1 2 3 4 >