Matches 1 - 46 out of 46
Match Document Document Title
7362715 Frame synchronization circuit  
Disclosed is a mobile communication system including a network constituted of at least one switching center and a plurality of base stations, and a mobile station which communicates with the base s...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstr...
7224705 Synchronization of a multi-mode base station using a common system clock  
A method for synchronizing a multi-mode base station using one clock, when the systems to be synchronized are a GSM-type telecommunications system, for instance a GSM or EDGE system, and a WCDMA-ty...
7187903 Method and apparatus for timing correction in communication systems  
In a wireless communications system, transceivers transmit short bursts to a base station, which determines timing corrections from the time of receipt of the burst and transmits the timing correct...
7168027 Dynamic synchronization of data capture on an optical or other high speed communications link  
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. ...
7159092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to stor...
7123628 Communication system with improved medium access control sub-layer  
A communication system which has a plurality of mobile terminals and a base station, each of the mobile terminals and/or base station comprising a medium access control sub-layer, upper layers of t...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data s...
7085294 Frame synchronization mechanism  
A mechanism for synchronizing transmission of frames in a telecommunications network including a mobile station, a radio network controller, at least one base station. The mobile station and each b...
7077333 Position-identifying coded pages  
A position-identifying coded page uses invisible codes to record relative position information. The page includes a page surface and a plurality of tags printed on the page surface in an ink that i...
7016451 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector ...
6959016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges  
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with r...
6954097 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The i...
6952462 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector ...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector ...
6912680 Memory system with dynamic timing correction  
A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the m...
6801989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to stor...
6778670 Method and apparatus for encryption and decryption  
A method and apparatus are provided for encrypting a stream of data transmitted within a frame. The method includes determining a first initialization state in a first preselected interval, and det...
6766945 Computer system interface surface with sensor having identifier  
A method and system for enabling user interaction with computer software running in a computer system. The user interaction is via an interface, such as a sheet of paper bearing information relatin...
6662304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a ...
6647523 Method for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the applie...
6643789 Computer system having memory device with adjustable data clocking using pass gates  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting ...
6601169 Key-based secure network user states  
A server and a computer are connected to a network. User data may be used to establish a state between a server and a user operating the computer. Key-based secure network user states includes encr...
6499111 Apparatus for adjusting delay of a clock signal relative to a data signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting ...
6496498 Method and system for avoiding periodic bursts of interference in wireless communication between a mobile unit and a base unit  
A method is provided for interfacing telecommunication devices. A base unit is connected to a landline for wireless communication. The base unit has a power supply operating at a power supply frequ...
6490224 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
6490207 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
6483757 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
6477675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data s...
6430696 Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same  
A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an ...
6400641 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
6389037 Arrangement for improving the architecture of mobile communication systems  
The present invention relates to an arrangement for improving the architecture of mobile communication systems, especially a telecommunications system, said system comprising distributed hardware a...
6378079 Computer system having memory device with adjustable data clocking  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting ...
6374360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a ...
6349399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the...
6340904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal  
A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal corres...
6338127 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same  
A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the resp...
6327196 Synchronous memory device having an adjustable data clocking circuit  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting ...
6304759 Method for extending the range of a wireless communication system  
A method for extending a cell radius or access range of a base station without incurring ASIC correlator re-design. This is accomplished using a modified timing protocol that will cause signals tra...
6279090 Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device  
A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the resp...
6269451 Method and apparatus for adjusting data timing by delaying clock signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting ...
6262921 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
6256259 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay li...
EP1035667A2 Communication methods and apparatus for controlling the transmission timing of a wireless transceiver  
In a wireless communications system, transceivers transmit short bursts to a base station, which determines timing corrections from the time of receipt of the burst and transmits the timing correct...
6029250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same  
A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to ...
6014375 TDMA radio protocol with adaptive vocoder selection  
A new air interface protocol compliant with narrowband (12.5 kHz) channels being mandated for use in North America provides a narrowband (i.e., 18 kbps-19.2 kbps), two-slot scaled version of the Eu...

Matches 1 - 46 out of 46