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7303938 Gated isolation structure for imagers  
Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of...
7294903 Transistor assemblies  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7291880 Transistor assembly  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7271464 Liner for shallow trench isolation  
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited...
7271463 Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base  
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited...
7259442 Selectively doped trench device isolation  
A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is...
7253047 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7141485 Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits  
A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The...
7112513 Sub-micron space liner and densification process  
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the...
7109571 Method of forming a hermetic seal for silicon die with metal feed through structure  
A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to...
7071531 Trench isolation for semiconductor devices  
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the...
7057257 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7005388 Method of forming through-the-wafer metal interconnect structures  
A semiconductor die is formed in a process that forms a hole through the wafer prior to the formation of the contacts and the metal-1 layer of an interconnect structure. The through-the-wafer hole...
6979651 Method for forming alignment features and back-side contacts with fewer lithography and etch steps  
The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a...
6914287 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
6856001 Trench isolation for semiconductor devices  
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the...
6835995 Low dielectric constant material for integrated circuit fabrication  
A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an...
6818930 Gated isolation structure for imagers  
Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of...
6781212 Selectively doped trench device isolation  
A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is...
6677235 Silicon die with metal feed through structure  
A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to...
6541349 Shallow trench isolation using non-conformal dielectric and planarizatrion  
A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with...
6508919 Optimized liners for dual damascene metal wiring  
A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an...
6383951 Low dielectric constant material for integrated circuit fabrication  
A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an...
6331456 Fipos method of forming SOI CMOS structure  
The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to...
6323101 Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers  
In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at...
6319796 Manufacture of an integrated circuit isolation structure  
Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an...
6270353 Low cost shallow trench isolation using non-conformal dielectric material  
A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with...
6221785 Method for forming shallow trench isolations  
A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on...
6177333 Method for making a trench isolation for semiconductor devices  
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the...
6175140 Semiconductor device using a shallow trench isolation  
In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a...
6140691 Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate  
A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active...
6087705 Trench isolation structure partially bound between a pair of low K dielectric structures  
A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment,...
6077771 Method for forming a barrier layer  
A procedure for forming the barrier layer includes a plasma procedure in the fabricating procedure. The procedure is that an opening is formed on a dielectric layer, which is formed over a...
5982008 Semiconductor device using a shallow trench isolation  
In a MOS transistor using shallow trench isolation, a patten of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a...
5943585 Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen  
A process is provided for forming a trench isolation structure which includes dielectric spacers composed of a dielectric material having a relatively low dielectric constant, K, that is...
5943575 Method of forming semiconductor device  
A method for fabricating a semiconductor device, including the steps of providing a semiconductor substrate of a first conductivity type, defining a channel region and source/drain regions in the...
Matches 1 - 36 out of 36