Matches 1 - 38 out of 38
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7376917 Client-server semiconductor verification system  
A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing...
7370237 Semiconductor memory device capable of accessing all memory cells  
A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a...
7276922 Closed-grid bus architecture for wafer interconnect structure  
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can...
7088117 Wafer burn-in and test employing detachable cartridge  
A cartridge ( 10 ) includes a chuck plate ( 12 ) for receiving a wafer ( 74 ) and a probe plate ( 14 ) for establishing electrical contact with the wafer. In use, a mechanical connecting device (...
7065723 Defect tracking by utilizing real-time counters in network computing environments  
Disclosed are novel methods and apparatus for manipulating and generating a real-time counter in network computing environments. In an embodiment, a method of tracking a defect is disclosed. The...
7057518 Systems and methods for testing wireless devices  
Systems and methods are disclosed for parallel testing one or more wireless devices using a single wireless command, each device including a processor and memory coupled to the processor. The...
6961674 System and method for analysis of cache array test data  
One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period...
6892328 Method and system for distributed testing of electronic devices  
A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test...
6842022 System and method for heterogeneous multi-site testing  
Disclosed are systems and methods which implement multi-site testing in which a test sequence implemented with respect to dice of a set of dice for parallel testing is not identical. Accordingly,...
EP1467379A1 Semiconductor memory device capable of accessing all memory cells  
A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a...
6754861 Circuitry for and system and substrate with circuitry for aligning output signals in massively parallel testers and other electronic devices  
Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
6703825 Separating device response signals from composite signals  
An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal...
6682945 Wafer level burn-in and electrical test system and method  
A burn-in and electrical test system ( 20 ) includes a temperature controlled zone ( 22 ) and a cool zone ( 24 ) separated by a transition zone 25. The temperature controlled zone ( 22 ) is...
6678850 Distributed interface for parallel testing of multiple devices using a single tester channel  
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester...
6651204 Modular architecture for memory testing on event based test system  
An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional...
6618836 Configuration and method for producing test signals for testing a multiplicity of semiconductor chips  
A configuration for producing test signals for testing semiconductor chips includes a clock signal source for producing a clock signal, and a tester. The test signals are produced on the respective...
6603323 Closed-grid bus architecture for wafer interconnect structure  
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can...
6580283 Wafer level burn-in and test methods  
A cartridge ( 10 ) includes a chuck plate ( 12 ) for receiving a wafer ( 74 ) and a probe plate ( 14 ) for establishing electrical contact with the wafer. In use, a mechanical connecting device (...
6563298 Separating device response signals from composite signals  
An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal...
6562636 Wafer level burn-in and electrical test system and method  
A burn-in and electrical test system ( 20 ) includes a temperature controlled zone ( 22 ) and a cool zone ( 24 ) separated by a transition zone 25. The temperature controlled zone ( 22 ) is...
6559671 Efficient parallel testing of semiconductor devices using a known good device to generate expected responses  
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the...
6556032 Wafer-burn-in and test employing detachable cartridge  
A cartridge ( 10 ) includes a chuck plate ( 12 ) for receiving a wafer ( 74 ) and a probe plate ( 14 ) for establishing electrical contact with the wafer. In use, a mechanical connecting device (...
6499121 Distributed interface for parallel testing of multiple devices using a single tester channel  
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester...
6480978 Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons  
What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester...
6452411 Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses  
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the...
6430725 System and method for aligning output signals in massively parallel testers and other electronic devices  
Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
6413113 Kinematic coupling  
A kinematic coupling includes a male connector ( 94 ) and first and second opposed jaws ( 122, 124 .) Each of the jaws is pivotable from a retracted position in which the male connector can be...
EP1195613A1 Functionality testing of programmed devices  
The test system 100 comprises a scheduler 110 storing a database 130 of tests to be run on units under test (UUTs), e.g. as part of a procedure for approving firmware. The tests are allocated to...
6367044 Semiconductor integrated circuit device  
In a semiconductor integrated circuit device, a pattern generator 12 generates burn-in test patterns based on control signals received through external terminals 11 and corresponding I/O...
6340895 Wafer-level burn-in and test cartridge  
A cartridge ( 10 ) includes a chuck plate ( 12 ) for receiving a wafer ( 74 ) and a probe plate ( 14 ) for establishing electrical contact with the wafer. In use, a mechanical connecting device (...
6292415 Enhancements in testing devices on burn-in boards  
A system for testing semiconductor devices on device test boards has a single tester channel connected to multiple DUTs in a loop. Outputs from DUTs are received at a comparator and latch after a...
6217367 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Kinematic coupling  
A kinematic coupling includes a male connector (94) and first and second opposed jaws (122, 124.) Each of the jaws is pivotable from a retracted position in which the male connector can be inserted...
6158030 System and method for aligning output signals in massively parallel testers and other electronic devices  
Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
6133725 Compensating for the effects of round-trip delay in automatic test equipment  
Improved pin electronics for automatic test equipment are disclosed which compensates for the effects of round-trip delay on signals transmitted by the pin electronics and a circuit under test...
6076179 Method and apparatus of increasing the vector rate of a digital test system  
The present invention provides a method and apparatus for increasing the vector rate of an integrated circuit test system and simplifying the wiring of the tester to the device under test. The...
5954832 Method and system for performing non-standard insitu burn-in testings  
A method and system for performing non-standard insitu burn-in testings is disclosed. In accordance with the method and system of the present invention, a transition counter is provided for each of...
5828824 Method for debugging an integrated circuit using extended operating modes  
A method of testing an integrated circuit 104 which may have multiple modules 204a-d is provided. Target interface 200 provides an interface for connecting target system 104 to a test system which...
5794175 Low cost, highly parallel memory tester  
Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test...
Matches 1 - 38 out of 38