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7403029 Massively parallel interface for electronic circuit  
Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated...
7394268 Carrier for test, burn-in, and first level packaging  
A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier...
7382142 High density interconnect system having rapid fabrication cycle  
An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA)...
7368812 Interposers for chip-scale packages and intermediates thereof  
A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar...
7349223 Enhanced compliant probe card systems having improved planarity  
Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that...
7329899 Wafer-level redistribution circuit  
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
7276400 Methods of making microelectronic packages with conductive elastomeric posts  
A method of making a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; providing a second...
7271491 Carrier for wafer-scale package and wafer-scale package including the carrier  
A carrier for use in a chip-scale package, including a semiconductor substrate, such as a semiconductor wafer, with a plurality of apertures formed therethrough. The present invention also includes...
7142000 Mounting spring elements on semiconductor devices, and wafer-level testing methodology  
Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies...
7132841 Carrier for test, burn-in, and first level packaging  
A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier...
7105366 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
7082682 Contact structures and methods for making same  
Contact structures are formed by building a core structure on a substrate and over coating the core structure with a material that is harder or has a greater yield strength than the material of the...
7074648 Method for packaging flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
7009412 Massively parallel interface for electronic circuit  
Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated...
7005878 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
6982177 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
6972495 Compliant package with conductive elastomeric posts  
An assembly including a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; a second microelectronic element having a top surface and a...
6972200 Method for manufacturing flip-chip semiconductor assembly  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6967494 Wafer-interposer assembly  
A wafer-interposer assembly ( 10 ) includes a semiconductor wafer ( 12 ) having a plurality of semiconductor die ( 14 ) that have a plurality of first electrical contact pads ( 16 ). An interposer...
6967113 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
6962826 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
6954081 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6953700 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6953699 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6949943 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6927083 Method for constructing a wafer-interposer assembly  
A method for reducing the likelihood of damaging a semiconductor wafer ( 18 ) and the integrated circuit chips of the semiconductor wafer ( 18 ) during handling utilizes a wafer interposer ( 12 )...
6909296 Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting  
A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any...
6884642 Wafer-level testing apparatus and method  
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
6881593 Semiconductor die adapter and method of using  
A semiconductor die adapter assembly includes a semiconductor die cut from a wafer, the die having an active surface including bond pads. A die adapter, also having bond pads, is bonded to the...
6844747 Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting  
A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any...
6818840 Method for manufacturing raised electrical contact pattern of controlled geometry  
Spring contact elements are attached to terminals of an electronic component, which may be a semiconductor die. The spring contact elements may comprise a flexible precursor element. The precursor...
6815961 Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies  
Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring...
6812048 Method for manufacturing a wafer-interposer assembly  
The present invention provides a wafer-interposer assembly apparatus and method. The method for manufacturing the wafer-interposer assembly including the steps of providing a semiconductor wafer...
6790684 Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing  
A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same are disclosed. The...
6744067 Wafer-level testing apparatus and method  
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
6655023 Method and apparatus for burning-in semiconductor devices in wafer form  
Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies...
6653208 Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing  
A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same is disclosed. The...
6577148 Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer  
A method, apparatus, and circuit distribution wafer (CDW) ( 16 ) are used to wafer-level test a product wafer ( 14 ) containing one or more product integrated circuits (ICs). The CDW ( 16 )...
6564351 Circuit and method for testing an integrated circuit  
A test mode detector ( 12 a ) that places a multi-pin integrated circuit ( 10 ) in test mode. The test mode detector ( 12 a ) comprises a pulse detector ( 25 ) that receives a control signal. The...
6541989 Testing device for semiconductor components and a method of using the device  
A testing device for semiconductor components and a method of making the device is described. The testing device includes a support structure having an outer edge, and an adhesive film disposed on...
6538214 Method for manufacturing raised electrical contact pattern of controlled geometry  
An interposer includes a substrate having opposing surfaces. Conductive terminals are disposed on both surfaces, and conductive terminals on one surface are electrically connected to conductive...
6411116 Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer  
A method, apparatus, and circuit distribution wafer (CDW) ( 16 ) are used to wafer-level test a product wafer ( 14 ) containing one or more product integrated circuits (ICs). The CDW ( 16 )...
6404063 Die-to-insert permanent connection and method of forming  
The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached...
6387714 Die-to-insert permanent connection and method of forming  
The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached...
6379982 Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing  
A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same. The wafer-on-wafer package...
6377897 Method and system for dynamic duration burn-in  
A computer-implemented method and system for dynamic duration burn-in. A computer system is provided having a processing unit, input device and storage. The storage includes a performance database...
6362637 Apparatus for testing semiconductor wafers including base with contact members and terminal contacts  
A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals...
6323663 Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method  
A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a...
6266794 Circuit and method for testing an integrated circuit  
A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control...
6245444 Micromachined element and method of fabrication thereof  
A micromachined element mounted to a substrate, the element including a cantilever having a proximal portion attached to the substrate and a coilable distal portion terminating in a free distal...
Matches 1 - 50 out of 81 1 2 >