Matches 1 - 35 out of 35
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7418071 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
7415404 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7307459 Programmable phase-locked loop circuitry for programmable logic device  
A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in...
7286007 Configurable clock network for programmable logic device  
In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7230495 Phase-locked loop circuits with reduced lock time  
PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled...
7190755 Phase-locked loop circuitry for programmable logic devices  
A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate...
7168027 Dynamic synchronization of data capture on an optical or other high speed communications link  
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver....
7159092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7075365 Configurable clock network for programmable logic device  
In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those...
7071743 Programmable phase-locked loop circuitry for programmable logic device  
A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in...
7042258 Signal generator with selectable mode control  
A signal generator circuit includes a controller adapted to generate a divide value in accordance with at least a first control signal, and a divider adapted to divide an output signal of the...
7019570 Dual-gain loop circuitry for programmable logic device  
A loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a...
7016451 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
7012984 PLL noise smoothing using dual-modulus interleaving  
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens”...
6959016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges  
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with...
6954097 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
6952462 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6924678 Programmable phase-locked loop circuitry for programmable logic device  
A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in...
6912680 Memory system with dynamic timing correction  
A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the...
6870409 Frequency synthesizer for reducing noise  
A fractional-N frequency synthesizer includes a first divider, a second divider, and a division ratio controller. The first divider receives and divides an oscillation frequency signal. The second...
6867616 Programmable logic device serial interface having dual-use phase-locked loop circuitry  
In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general...
6643347 Clock signal generation apparatus  
A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. A first oscillator generates a reference clock signal having a...
6236278 Apparatus and method for a fast locking phase locked loop  
A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation....
6028493 Elimination of bandpass filter after quadrature modulator in modulation synthesizer circuit  
A modulation synthesizer circuit produces a fixed intermediate frequency unmodulated signal without harmonics aliasing back into the transmit spectrum, thus, eliminating the need for a bandpass...
6006078 Receiver with improved lock-up time and high tuning stability  
A receiver has an oscillator for generating an oscillating signal at an oscillating frequency in accordance with an oscillation control signal, and receives a radio signal at a tuning frequency...
5907253 Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element  
A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals...
5889436 Phase locked loop fractional pulse swallowing frequency synthesizer  
A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but...
5739727 Sampled phase locked loop being locked with support from another phase locked loop  
A sampled phase locked loop is phase-locked with support from a conventional phase locked loop (PLL). The support value from the PLL is locked with the aid of a sample and hold circuit. The locked...
5694089 Fast frequency switching synthesizer  
This is a PLL frequency synthesizer having a reference divider for dividing a reference source signal, and an RF divider for dividing the output of a voltage controlled oscillator, wherein when...
5499393 Receiver with function to adjust local frequency following reception frequency  
A receiver which has a linear approximation expression showing a relationship between the frequency deviations and corresponding changes to the voltage which is to be supplied to the voltage...
5486792 Method and apparatus for calculating a divider in a digital phase lock loop  
A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital...
Matches 1 - 35 out of 35