Matches 1 - 50 out of 125 1 2 3 >
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7418071 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
7415404 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7168027 Dynamic synchronization of data capture on an optical or other high speed communications link  
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver....
7159092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7069406 Double data rate synchronous SRAM with 100% bus utilization  
A synchronous memory circuit is capable of double data transfer rate per clock cycle, 100% bus utilization (i.e., no idle clock cycles in bus turn arounds), and has only one clock cycle of latency...
7068067 Semiconductor circuit device having active and standby states  
A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node...
7016451 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6959016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges  
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with...
6954097 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
6952462 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6912680 Memory system with dynamic timing correction  
A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the...
6885216 Semiconductor circuit device having active and standby states  
A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node...
6801989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
6789175 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6662304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a...
6647523 Method for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the...
6643789 Computer system having memory device with adjustable data clocking using pass gates  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
EP0740861B1 BREAKDOWN PROTECTION CIRCUIT USING HIGH VOLTAGE DETECTION  
Abstract not available
6614698 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6611885 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6591354 Separate byte control on fully synchronous pipelined SRAM  
A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each...
6569727 Method of making a single-deposition-layer-metal dynamic random access memory  
A 16 megabit (2 24 ) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide...
6567338 Fully synchronous pipelined RAM  
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be...
6560668 Method and apparatus for reading write-modified read data in memory device providing synchronous data transfers  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6556483 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6519719 Method and apparatus for transferring test data from a memory array  
A memory device includes an output data path that uses single-ended data in conjunction with a flag signal. The output data path transfers data from an I/O circuit coupled to a memory array to an...
6515885 Tri-stating address input circuit  
An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address...
6499111 Apparatus for adjusting delay of a clock signal relative to a data signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6490224 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6490207 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6483757 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6477675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
6459301 Semiconductor circuit device having active and standby states  
A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node...
6437600 Adjustable output driver circuit  
An adjustable integrated circuit output driver circuit is described which has a push-pull output circuit comprised of a pullup and pulldown transistor. A series of parallel transistors are...
6430696 Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same  
A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an...
6415340 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths  
A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and...
6407939 Single deposition layer metal dynamic random access memory  
A system and method for forming a memory having at least 16 megabits (2 24 bits) and only a single deposition layer of highly conductive interconnects. The resulting semiconductor die or chip fits...
6405280 Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence  
A system and method for providing a burst sequence of data in a desired data ordering in response to a request packet. The burst sequence of data includes a plurality of data blocks and the request...
6400641 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6393378 Circuit and method for specifying performance parameters in integrated circuits  
A method and circuit for recording the performance parameters in an integrated circuit. A speed grade register is programmed by the manufacturer with an indication of the speed capability of the...
6388314 Single deposition layer metal dynamic random access memory  
A 16 megabit (2 24 ) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide...
6378079 Computer system having memory device with adjustable data clocking  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6374360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a...
6349399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the...
6345012 Tri-stating address input circuit  
An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address...
6340904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal  
A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal...
Matches 1 - 50 out of 125 1 2 3 >