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7433751 Sorting a group of integrated circuit devices for those devices requiring special testing  
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing...
7405463 Gate dielectric antifuse circuit to protect a high-voltage transistor  
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric...
7402855 Split-channel antifuse array architecture  
Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application....
7368678 Method for sorting integrated circuit devices  
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of...
7279918 Methods for wafer level burn-in  
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in each IC die in nonvolatile elements...
7276672 Method for sorting integrated circuit devices  
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of...
7260125 Method of forming mirrors by surface transformation of empty spaces in solid state materials  
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by...
7247879 Semiconductor integrated circuit device having particular testing pad arrangement  
In a semiconductor integrated circuit device, testing pads ( 209 b ) using a conductive layer, such as relocation wiring layers ( 205 ) are provided just above or in the neighborhood of terminals...
7215134 Apparatus for determining burn-in reliability from wafer level burn-in  
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in...
7206215 Antifuse having tantalum oxynitride film and method for making same  
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen...
7194667 System for storing device test information on a semiconductor device using on-device logic for determination of test results  
A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which...
7164188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials  
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the...
7155300 Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs  
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be...
7146585 Programmable element latch circuit  
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a...
7142577 Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon  
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by...
7132348 Low k interconnect dielectric using surface transformation  
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment...
7126871 Circuits and methods to protect a gate dielectric antifuse  
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a...
7124050 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture  
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic...
7120513 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs  
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be...
7120287 Non-lot based method for assembling integrated circuit devices  
An inventive method tracks IC devices through the assembly steps in a manufacturing process. Prior to die attach, a laser scribe marks the lead frame of each of the devices with a coded hole matrix...
7119568 Methods for wafer level burn-in  
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in each IC die in nonvolatile elements...
7117063 Sorting a group of integrated circuit devices for those devices requiring special testing  
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing...
7115967 Three-dimensional memory  
A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.
7107117 Sorting a group of integrated circuit devices for those devices requiring special testing  
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing...
7101738 Gate dielectric antifuse circuit to protect a high-voltage transistor  
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric...
7081377 Three-dimensional memory  
A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.
7071534 Antifuse structure and method of use  
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a...
7038481 Method and apparatus for determining burn-in reliability from wafer level burn-in  
A method and apparatus for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC...
7038265 Capacitor having tantalum oxynitride film and method for making same  
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen...
7034560 Device and method for testing integrated circuit dice in an integrated circuit module  
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate...
7030458 Gate dielectric antifuse circuits and methods for operating same  
A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an...
6991970 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device  
A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically...
6979880 Scalable high performance antifuse structure and process  
Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric...
6944567 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture  
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic...
6943575 Method, circuit and system for determining burn-in reliability from wafer level burn-in  
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in...
6943065 Scalable high performance antifuse structure and process  
Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric...
6936909 Gate dielectric antifuse circuit to protect a high-voltage transistor  
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric...
6928596 Test circuit of semiconductor integrated circuit  
A test code is input to a test mode control circuit so that the test mode control circuit creates the test decode signal. The test decode signal is converted into serial data with a...
6897542 Semiconductor assemblies  
The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending...
6894526 Apparatus for determining burn-in reliability from wafer level burn-in  
An apparatus for determining burn-in reliability from wafer level burn-in is disclosed. The apparatus according to the present invention includes nonvolatile elements on an integrated circuit for...
6875641 Three-dimensional memory  
A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.
6836000 Antifuse structure and method of use  
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a...
6833291 Semiconductor processing methods  
The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending...
6831294 Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes  
In a semiconductor integrated circuit device, testing pads ( 209 b ) using a conductive layer, such as relocation wiring layers ( 205 ) are provided just above or in the neighborhood of terminals...
6829737 Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results  
A method and system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic...
6816427 Method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories  
A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated...
6812122 Method for forming a voltage programming element  
Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first...
6801048 Device and method for testing integrated circuit dice in an integrated circuit module  
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate...
6775197 Non-volatile memory element integratable with standard CMOS circuitry and related programming methods and embedded memories  
A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS...
6775171 Method of utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements and related embedded memories  
A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated...
Matches 1 - 50 out of 117 1 2 3 >