Matches 1 - 16 out of 16
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7370306 Method and apparatus for designing a pattern on a semiconductor surface  
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
7290242 Pattern generation on a semiconductor surface  
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
7259464 Vertical twist scheme for high-density DRAMs  
An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and...
6946353 Low voltage high performance semiconductor devices and methods  
A method for adjusting V t while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant...
6934928 Method and apparatus for designing a pattern on a semiconductor surface  
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
6898779 Pattern generation on a semiconductor surface  
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a...
6867148 Removal of organic material in integrated circuit fabrication using ozonated organic acid solutions  
Organic acid components are used to increase the solubility of ozone in aqueous solutions for use in removing organic materials, such as polymeric resist and/or post-etch residues, from the surface...
6812075 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same  
A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a...
6747326 Low voltage high performance semiconductor device having punch through prevention implants  
A method for adjusting V t while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant...
6583469 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same  
A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a...
6492693 Low voltage high performance semiconductor devices and methods  
A method for adjusting V t while minimizing parasitic capacitance fiord low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant...
6312997 Low voltage high performance semiconductor devices and methods  
A method for adjusting V t while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant...
6057198 Semiconductor processing method of forming a buried contact  
A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief...
5773346 Semiconductor processing method of forming a buried contact  
A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief...
5300444 Method of manufacturing a semiconductor device having a stacked structure formed of polycrystalline silicon film and silicon oxide film  
A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon...
5189595 Edge shrinkage compensated devices  
Improved, edge compensated capacitors and a method for making the same are presented. The present invention arranges individual cells of capacitors and uses passive dummy cells so as to achieve a...
Matches 1 - 16 out of 16