Matches 1 - 37 out of 37
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7151785 Optoelectronic devices and methods of production  
The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top...
6864129 Double gate MOSFET transistor and method for the production thereof  
A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material...
6747314 Method to form a self-aligned CMOS inverter using vertical device integration  
A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is...
EP0700093B1 Semiconductor device and method of manufacturing the same  
Abstract of EP0700093 On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first...
6724798 Optoelectronic devices and method of production  
The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top...
6518112 High performance, low power vertical integrated CMOS devices  
A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates...
6515348 Semiconductor device with FET MESA structure and vertical contact electrodes  
A semiconductor device comprises one or more field effect devices (FD) having source and drain regions ( 5 and 6 ) spaced apart by a body region ( 3 a ). A gate structure ( 7 a , 7 b ),...
6515330 Power device having vertical current path with enhanced pinch-off for current limiting  
A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain...
6444527 Method of operation of punch-through field effect transistor  
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region...
6426530 High performance direct coupled FET memory cell  
A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of...
EP0763259B1 PUNCH-THROUGH FIELD EFFECT TRANSISTOR  
Abstract not available for EP0763259 Abstract of corresponding document: US5592005 A trenched field effect transistor suitable especially for low voltage power applications provides low leakage...
6344381 Method for forming pillar CMOS  
A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then...
6297531 High performance, low power vertical integrated CMOS devices  
A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates...
6268621 Vertical channel field effect transistor  
A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial...
6255699 Pillar CMOS structure  
A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then...
6204532 Pillar transistor incorporating a body contact  
According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed...
6188105 High density MOS-gated power device and process for forming same  
A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source...
6137129 High performance direct coupled FET memory cell  
A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of...
6100123 Pillar CMOS structure  
A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then...
6069043 Method of making punch-through field effect transistor  
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region...
6020239 Pillar transistor incorporating a body contact  
According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed...
EP0656647B1 Method of fabricating an integrated circuit device comprising at least a MOS transistor  
Abstract not available for EP0656647 Abstract of corresponding document: US5443992 An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first...
5670810 Semiconductor device with a vertical field effect transistor  
On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon...
EP0763259A1 PUNCH-THROUGH FIELD EFFECT TRANSISTOR  
Abstract not available for EP0763259 Abstract of corresponding document: US5592005 A trenched field effect transistor suitable especially for low voltage power applications provides low leakage...
EP0700093A1 Semiconductor device and method of manufacturing the same  
On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon...
5455435 Late programming mask ROM and process for producing the same  
A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon...
5443992 Method for manufacturing an integrated circuit having at least one MOS transistor  
An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is...
EP0656647A1 Method of fabricating an integrated circuit device comprising at least a MOS transistor.  
Abstract not available for EP0656647 Abstract of corresponding document: US5443992 An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first...
5416736 Vertical field-effect transistor and a semiconductor memory cell having the transistor  
The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a...
5398200 Vertically formed semiconductor random access memory device  
A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical...
5364810 Methods of forming a vertical field-effect transistor and a semiconductor memory cell  
The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a...
5293053 Elevated CMOS  
A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is...
5291058 Semiconductor device silicon via fill formed in multiple dielectric layers  
A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a...
5283456 Vertical gate transistor with low temperature epitaxial channel  
A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon...
5250828 Structure of semiconductor memory device  
A semiconductor memory device has a stacked capacitor cell structure which is composed of two MIS transistors and one capacitor. One MIS transistor is formed between a charge accumulation electrode...
5219793 Method for forming pitch independent contacts and a semiconductor device having the same  
A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor...
EP0149680B1 APPARATUS FOR DETECTING SPEED OF ELECTRIC MOTOR  
Abstract not available for EP0149680 Abstract of corresponding document: US4551662 PCT No. PCT/JP84/00358 Sec. 371 Date Mar. 6, 1985 Sec. 102(e) Date Mar. 6, 1985 PCT Filed Jul. 11, 1984 PCT Pub....
Matches 1 - 37 out of 37