Matches 1 - 36 out of 36
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EP1830241B1 Integrated circuit I/O using a high performance bus interface  
7209997 Controller device and method for operating same  
A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The...
EP1022641B1 System containing a plurality of DRAMS and a bus  
Abstract not available for EP1022641 Abstract of corresponding document: EP0994420 The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17),...
EP1197830B1 Integrated circuit I/O using a high performance bus interface  
Abstract not available for EP1197830
7110322 Memory module including an integrated circuit device  
A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device...
6975558 Integrated circuit device  
An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control...
6807598 Integrated circuit device having double data rate capability  
A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output...
6751696 Memory device having a programmable register  
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus...
6728819 Synchronous memory device  
A synchronous semiconductor memory device including a memory cell array and a plurality of input receivers to sample address information synchronously with respect to a clock signal. The address...
6715020 Synchronous integrated circuit device  
A controller device for controlling a synchronous dynamic random access memory device. The controller device includes output driver circuitry to output block size information to the memory device....
6697295 Memory device having a programmable register  
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus...
6684285 Synchronous integrated circuit device  
An integrated circuit device that includes a clock synchronization circuit. The clock synchronization circuit receives an external clock signal and generates an internal clock signal from the...
6584037 Memory device which samples data after an amount of time transpires  
A method of operation of a synchronous memory device. The memory device includes an array of dynamic random access memory cells. The method of operation of the memory device includes receiving an...
6570814 Integrated circuit device which outputs data after a latency period transpires  
An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a...
6564281 Synchronous memory device having automatic precharge  
A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device...
6546446 Synchronous memory device having automatic precharge  
A synchronous integrated circuit memory device including an array of memory cells. The memory device includes a clock receiver to receive an external clock signal, and a plurality of sense...
6415339 Memory device having a plurality of programmable internal registers and a delay time register  
A synchronous memory device and a method of controlling the memory device. The memory device including at least one memory section having a plurality of memory cells. The memory device includes a...
6378020 System having double data transfer rate and intergrated circuit therefor  
A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry...
EP1197830A2 Integrated circuit I/O using a high performance bus interface  
Abstract not available for EP1197830
6346823 Pulse generator for providing pulse signal with constant pulse width  
A pulse generator for providing a pulse signal with a constant pulse width. An edge detection unit, coupled between a node and a ground terminal, detects an edge of an external clock to set a node...
6314051 Memory device having write latency  
A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to...
6304937 Method of operation of a memory controller  
A method of operation of a memory controller device, the method of operation comprises issuing a write request to a memory device synchronously with respect to an external clock signal, wherein in...
EP1022642B1 Integrated circuit I/O using a high performance bus interface  
Abstract of EP1022642 The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected...
6266285 Method of operating a memory device having write latency  
A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write...
6182184 Method of operating a memory device having a variable data input length  
A method of controlling a memory device. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to...
EP1022642A1 Integrated circuit I/O using a high performance bus interface  
The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the...
EP1022641A1 Integrated circuit i/o using a high performance bus interface  
Abstract not available for EP1022641 Abstract of corresponding document: EP0994420 The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17),...
EP0994420A2 Integrated circuit i/o using a high performance bus interface  
The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the...
6051988 Pulse width controlling logic circuit  
An input pulse signal is applied to an input terminal of a pulse width controlling logic circuit and integrated by an integrating circuit. A desired output signal is obtained at an output terminal...
5682355 Address transition detection (ATD) circuit  
An address transition detection (ATD) circuit for use in a memory generates a first pulse in a first node in response to a change in state of an address signal and generates a second pulse in a...
5590089 Address transition detection (ATD) circuit  
An address transition detection (ATD) circuit for use in a memory generates a first pulse in a first node in response to a change in state of an address signal and generates a second pulse in a...
5455803 Semiconductor device which operates at a frequency controlled by an external clock signal  
A semiconductor memory device includes a memory cell array, an address part for supplying address signals to the memory cell array, a read/write part for reading data from the memory cell array and...
5426390 Circuit for generating input transition detection pulse  
In input transition detection pulse generators used in semiconductor memory devices, etc., in order to permit a designer to arbitrarily design the power supply voltage dependency of an output pulse...
5371780 Communications resource assignment in a wireless telecommunications system  
Fast resource assignments, especially needed in microcellular network architectures having many fast moving subscribers and high traffic volume, is provided through the use of a priority based...
5264737 One-shot signal generation circuitry for use in semiconductor memory integrated circuit  
An OS signal generation circuitry comprises a plurality of OS signal generating circuits receiving corresponding address bits of an address so as to generate individual OS signals, respectively,...
5199002 SRAM-address-change-detection circuit  
For enabling a static, random-access-memory (500) bit lines (556 and 558) pre-charging circuit (518), employed is an address-change-detection circuit (510) having a plurality of...
Matches 1 - 36 out of 36