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7418071 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
7415404 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7292486 Methods and circuits for latency control in accessing memory devices  
Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in...
7234070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7215175 Fuse sensing scheme with auto current reduction  
An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one...
7177207 Sense amplifier timing  
Systems and methods provide sense amplifier timing techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of memory cells and...
7168027 Dynamic synchronization of data capture on an optical or other high speed communications link  
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver....
7159092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7016451 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6959016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges  
A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with...
6954097 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
6952462 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6937536 Antifuse option for row repair  
A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6912680 Memory system with dynamic timing correction  
A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the...
6801989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same  
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to...
6680520 Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses  
The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit...
6662304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a...
EP0798744B1 Timing characterization circuit and method for memory devices  
Abstract of EP0798744 The circuit (2) includes a memory element (33) connected to an enabling input (15) receiving an enabling signal (ATD), and in turn including a first reset circuit (45)...
EP0798741B1 Data sensing timing modulating circuit, particularly for non-volatile memories  
Abstract of EP0798741 A data sensing timing modulating circuit, particularly for non-volatile memories, the particularity whereof is that it comprises means (1) for generating a first voltage...
6647523 Method for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the...
6643789 Computer system having memory device with adjustable data clocking using pass gates  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6515933 Semiconductor device and semiconductor storage device testing method  
In a variable resistance circuit included in a internal power supply potential generation circuit of a DRAM, to a fuse for tuning an internal power supply potential, an N channel MOS transistor is...
6499111 Apparatus for adjusting delay of a clock signal relative to a data signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6496053 Corrosion insensitive fusible link using capacitance sensing for semiconductor devices  
A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link...
6490224 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6490207 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6483757 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6477675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
6430696 Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same  
A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an...
6400641 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6378079 Computer system having memory device with adjustable data clocking  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6374360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus  
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a...
6349399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the...
6340904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal  
A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal...
6338127 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same  
A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the...
6327196 Synchronous memory device having an adjustable data clocking circuit  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6310506 Programmable setup/hold time delay network  
A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable...
6279090 Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device  
A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the...
6269451 Method and apparatus for adjusting data timing by delaying clock signal  
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting...
6262921 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6256259 Delay-locked loop with binary-coupled capacitor  
A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay...
6201424 Synchronous clock generator including a delay-locked loop signal loss detector  
A loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal, is comprised of a first monitor for receiving a...
6185135 Robust wordline activation delay monitor using a plurality of sample wordlines  
A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and...
6173432 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
6119242 Synchronous clock generator including a false lock detector  
A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and...
6115318 Clock vernier adjustment  
A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the...
6115310 Wordline activation delay monitor using sample wordline located in data-storing array  
A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or...
Matches 1 - 50 out of 82 1 2 >