|
Match
|
Document |
Document Title |
|
|
7372741 |
Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit...
|
|
|
7369435 |
Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic...
|
|
|
7348237 |
NOR flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The...
|
|
|
7257022 |
Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor...
|
|
|
7221586 |
Memory utilizing oxide nanolaminates
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a...
|
|
|
7221017 |
Memory utilizing oxide-conductor nanolaminates
Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a...
|
|
|
7193893 |
Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic...
|
|
|
7166509 |
Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic...
|
|
|
7154778 |
Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor...
|
|
|
7133315 |
Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect...
|
|
|
7130220 |
Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic...
|
|
|
7113429 |
Nor flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The...
|
|
|
7112494 |
Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect...
|
|
|
7099199 |
Nonvolatile semiconductor memory device
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit...
|
|
|
7020028 |
Nonvolatile semiconductor memory device
An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith....
|
|
|
6996009 |
NOR flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The...
|
|
|
6936527 |
Low voltage non-volatile memory cell
A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal...
|
|
|
6930920 |
Low voltage non-volatile memory cell
A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal...
|
|
|
6909635 |
Programmable memory cell using charge trapping in a gate oxide
An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET)...
|
|
|
6888739 |
Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor...
|
|
|
6804136 |
Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect...
|
|
|
6791882 |
Nonvolatile semiconductor memory device
An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith....
|
|
|
6747902 |
Nonvolatile semiconductor memory apparatus
A nonvolatile memory apparatus contains plural memories, at least one of which is a nonvolatile memory, and a processing unit. Data input/output (I/O) terminals of the memories and processing unit...
|
|
|
6545314 |
Memory using insulator traps
A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as...
|
|
|
6534998 |
Semiconductor device and control method thereof
Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations...
|
|
|
6438036 |
Nonvolatile semiconductor memory device
An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith....
|
|
|
6351411 |
Memory using insulator traps
A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as...
|
|
|
6271560 |
Single-poly EPROM cell with CMOS compatible programming voltages
The Frohmann-Bentchkowsky EPROM cell is programmed by utilizing biasing voltages which are sufficient to induce hot punchthrough holes to flow from the source region to the drain region, and...
|
|
|
6259629 |
Nonvolatile semiconductor memory device
Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least...
|
|
|
6246606 |
Memory using insulator traps
A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as...
|
|
|
6181600 |
Nonvolatile semiconductor memory device
Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least...
|
|
|
6157576 |
Nonvolatile semiconductor memory device
Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least...
|
|
|
6137724 |
Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel...
|
|
|
6137723 |
Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure
A memory device has a plurality of memory cells formed in rows and columns. Each memory cell includes an erasable Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access...
|
|
|
6137722 |
Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors
A plurality of Frohmann-Bentchkowsky p-channel memory transistors which are arranged in rows and columns is disclosed. Each column of memory transistors has an associated output line. A row of...
|
|
|
6137721 |
Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure
A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes an erasable Frohmann-Bentchkowsky p-channel memory transistor and an...
|
|
|
6130840 |
Memory cell having an erasable Frohmann-Bentchkowsky memory transistor
A memory cell has an erasable Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. Eraseability is provided by utilizing a p-well which is formed adjacent to...
|
|
|
6128223 |
Semiconductor memory device
A semiconductor memory device includes a memory cell and first and second electrodes. The memory cell has a floating gate formed on a semiconductor substrate via a gate insulating film to be...
|
|
|
5898614 |
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device comprises a plurality of memory cells each including a semiconductor substrate of a first conductivity type having a main surface region, a control gate...
|
|
|
5844842 |
Nonvolatile semiconductor memory device
Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least...
|
|
|
5691939 |
Triple poly PMOS flash memory cell
A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin runnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin...
|
|
|
EP0517607B1 |
Method of fabrication of a non-volatile memory cell and memory cell fabricated with this method
Abstract of EP0517607 This method consists in producing strips in a stack of an insulating layer and of a conductive layer intended to form respectively the gate insulators (210) and the floating...
|
|
|
EP0520825B1 |
Process for the simultaneous fabrication of high- and low voltage semiconductor devices, integrated circuit containing the same, systems and methods
Abstract of EP0520825 An electrically-erasable, electrically-programmable read-only memory cell (676) is formed at a face of a semiconductor layer (152) having a first conductivity-type and...
|
|
|
5465231 |
EEPROM and logic LSI chip including such EEPROM
Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate...
|
|
|
EP0623959A2 |
EEPROM cell.
An EEPROM cell has a first MOS transistor formed in a semiconductor substrate 1 of a first conductivity type and having current conducting regions 2a, 2b of a second conductivity type and a gate...
|
|
|
5301150 |
Flash erasable single poly EPROM device
A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor...
|
|
|
5291052 |
CMOS semiconductor device with (LDD) NMOS and single drain PMOS
A MOS semiconductor device and the methods for constructing the device. The MOS device provided with first and second MOS transistors are formed on two identical wafer sections. The impurity region...
|
|
|
5256584 |
Method for producing a non-volatile memory cell using spacers
Method for producing a non-volatile memory cell and obtained memory cell. This method consists of embodying strips in a stacking of one nonconducting film and one conductive film, both films...
|
|
|
5253200 |
Electrically erasable and programmable read only memory using stacked-gate cell
An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or the same as an UV-EPROM. Erasure operating is...
|
|
|
5225700 |
Circuit and method for forming a non-volatile memory cell
An electrically-erasable, electrically-programmable read-only memory cell (676) is formed at a face of a semiconductor layer (152) having a first conductivity-type and includes a tunnel diode doped...
|