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7350008 Electronic system having modular expansion function facilities  
An electronic system supporting modular expansion of its functions is of a type including a portable host electronic device associated with an expansion module adapted for quick-connect engagement...
7287113 Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure  
An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform...
7162653 Electric power distribution center having a plurality of ASICS each with a voltage to frequency converter that use an RMS current value  
An electrical power distribution system is disclosed that includes a gateway module ( 100 ) including logic ( 112 ) to interface to a vehicle management computer (VMC) ( 50 ) via a dual redundant...
7145921 Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure  
An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register...
7103700 Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure  
An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform...
7020790 Electric load management center including gateway module and multiple load management modules for distributing power to multiple loads  
An electrical distribution system is disclosed that includes a gateway module ( 100 ) including logic ( 112 ) to interface to a vehicle management computer (VMC) ( 50 ) via a dual redundant...
7007179 Electric load management center  
An electrical power distribution system is disclosed that includes a gateway module ( 100 ) including logic ( 112 ) to interface to a vehicle management computer (VMC) ( 50 ) via a dual redundant...
6904475 Programmable first-in first-out (FIFO) memory buffer for concurrent data stream handling  
A programmable FIFO receives a stream of data to be buffered within the FIFO and then output from the FIFO. The programmable FIFO includes the ability to receive program instructions from an...
6813531 Method, system, and article of manufacture for product configuration  
Provided are a method, system, and article of manufacture for product configuration. Order information is received for a product. Based on the received order information, configuration information...
6631435 Application programming interface for data transfer and bus management over a bus structure  
In a first embodiment, an applications programming interface (API) implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an...
6587910 Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure  
An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform...
6523108 Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string  
Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a...
6519268 Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure  
An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register...
6505268 Data distribution in a disk array  
For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon...
6496860 Media manager for controlling autonomous media devices within a network environment and managing the flow and format of data between the devices  
A media manager provides data flow management and other services for client applications on devices coupled together within a network. Preferably, these devices are coupled together within an IEEE...
6493753 Media manager for controlling autonomous media devices within a network environment and managing the flow and format of data between the devices  
A media manager provides data flow management and other services for client applications on devices coupled together within a network. Preferably, these devices are coupled together within an IEEE...
6463529 Processor based system with system wide reset and partial system reset capabilities  
A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The...
6314515 Resetting multiple processors in a computer system  
Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the...
6243783 Application programming interface for managing and automating data transfer operations between applications over a bus structure  
An applications programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asyncronous transfer the API...
6233637 Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure  
An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform...
6233611 Media manager for controlling autonomous media devices within a network environment and managing the flow and format of data between the devices  
A media manager provides data flow management and other services for client applications on devices coupled together within a network. Preferably, these devices are coupled together within an IEEE...
6119185 Computer system configuration apparatus and method that performs pre-assignment conflict analysis  
Self-configuring computer apparatus and method thereof. The computer apparatus preferably includes logic that determines the available system resources and those devices that desire access to those...
6072543 Priority order processing circuit and method for an MPEG system  
A priority order processing circuit is disclosed for an MPEG system adapted to determine the priority order of events generated from a multiprocessor of a decoding system utilizing MPEG1 and MPEG2...
6049870 System and method for identifying and configuring modules within a digital electronic device  
A system and method for identifying and configuring modules within a digital electronic device comprises a coordinator device coupled to the electronic device, functional modules coupled to the...
5909691 Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array  
For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon...
5870602 Multi-processor system with system wide reset and partial system reset capabilities  
A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a...
5867703 Common reset ROM  
Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the...
5864715 System for automatically terminating a daisy-chain peripheral bus with either single-ended or differential termination network depending on peripheral bus signals and peripheral device interfaces  
A peripheral device interface is coupled between a computer system bus and a peripheral bus. The peripheral device bus includes a signal line which can be configured in either a single-ended or a...
5862375 System for effecting communications between a computing device and a plurality of peripheral devices  
A system for effecting communications between a computing device and a plurality of peripheral devices which comprises a bus controller for controlling the communications, a plurality of feedback...
5784632 Parallel diagonal-fold array processor  
A massively parallel processor apparatus having an instruction set architecture for each of the N 2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of...
5754886 Controller for supplying multiplexed or non-multiplexed address signals to different types of dynamic random access memories  
A dynamic random access memory (RAM) addressing controller comprises a plurality of connectors connectible with a plurality of memory boards which use different addressing arrangements. A timing...
5729675 Apparatus for initializing a multiple processor computer system using a common ROM  
Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the...
5708831 Method of bus address assignment  
To connect the various stations of a data processing system, a bus system is used, to which all users have access. In accordance with the invention, a method for automatic assignment of bus...
5701422 Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses  
A mechanism for ensuring coherency between a system memory and a cache memory within a processing system including a first split transaction bus, the system memory being connected to the first...
5655106 Personal computer with riser connector for expansion bus and alternate master  
Alternate focal bus mastering and expansion bus capability are provided for a Family I computer system where an alternate bus master and expansion or input/output bus are connectable to the...
5625832 Distributed processing control method and distributed processing system  
A distributed control method and distributed processing system to decrease data communication overhead and to execute a program efficiently. One of processors at which data arrives in a...
5625796 Method and apparatus for concurrently accessing multiple memories with different timing requirements  
A data processing system in which a plurality of processors or other memory access devices operate either synchronously or asynchronously with a memory interface device, which in turn provides...
5597244 Electronic typewriter with spell verify  
A spell verification method and apparatus which comprises inputting characters and operational modes by keystrokes, printing input characters, providing a read only memory having plural...
5596759 Method for initializing a multiple processor computer system using a common ROM  
Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the...
5592648 Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array  
For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon...
5561813 Circuit for resolving I/O port address conflicts  
An input/output port address selection circuit for a device that couples to a local bus of a computer operates in two modes. In a first mode, the I/O port address is maintained as the last I/O port...
5553290 Software packaging structure having hierarchical replaceable units  
A software management structure is disclosed. A software application package is made up of several linked replaceable units (RU). Each RU is serviceable without adversely effecting the other RUs....
5553247 Method for unblocking a multibus multiprocessor system  
In the field of multiprocessor systems of the type including at least one processing module made up of processors which are connected to a main bus or several processing modules which communicate...
5530838 Method and apparatus for controlling access to memory which is common to plural, priority-ordered central processing units and which is indirectly accessible via a transfer control unit  
There is provided a common-memory controlling apparatus which controls data transfer between a common-memory and a plurality of central processing units. A separating buffer separates a CPU bus...
5522064 Data processing apparatus for dynamically setting timings in a dynamic memory system  
A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The...
5507002 Peripheral component interconnect special cycle protocol using soft message IDS  
A Peripheral Component Interconnect (PCI) bus provides component level interconnection of processors, peripherals and memories. A bus protocol mechanism includes a Special Cycle command for...
5497497 Method and apparatus for resetting multiple processors using a common ROM  
Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining,...
5491804 Method and apparatus for automatic initialization of pluggable option cards  
A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a...
5454111 Double unequal bus timeout  
A method and arrangement for preventing the locking out of devices which are coupled to a bus by either of two of the devices which have become initiator and target devices respectively. The...
5440716 Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array  
For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon...
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