Matches 1 - 50 out of 183 1 2 3 4 >
Match Document Document Title
7395332 Method and apparatus for high-speed parsing of network messages  
A method for searching network messages for pre-defined regular expressions is disclosed. A plurality of pre-defined regular expressions are stored in a content-addressable memory (CAM). A network...
7307956 Multi-protocol telecommunications routing optimization  
A telecommunications switching system employing multi-protocol routing optimization which utilizes predetermined and measured parameters in accordance with a set of user priorities in determining...
7185224 Processor isolation technique for integrated multi-processor systems  
A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point...
6920562 Tightly coupled software protocol decode with hardware data encryption  
An encryption mechanism tightly-couples hardware data encryption functions with software-based protocol decode processing within a pipelined processor of a programmable processing engine....
6892237 Method and apparatus for high-speed parsing of network messages  
A programmable pattern matching engine efficiently parses the contents of network messages for regular expressions and executes pre-defined actions or treatments on those messages that match the...
6804244 Integrated circuits for packet communications  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate...
6801532 Packet reconstruction processes for packet communications  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate (s...
6801499 Diversity schemes for packet communications  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate (s...
6765904 Packet networks  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate (s...
6757256 Process of sending packets of real-time information  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate (s...
6744757 Private branch exchange systems for packet communications  
A process ( 111,101 ) of sending packets of real-time information at a sender ( 311 ) includes steps of initially generating at the sender the packets of real-time information with a source rate (s...
6741552 Fault-tolerant, highly-scalable cell switching architecture  
Generally speaking, the cell switching architecture of the present invention offers a powerful, simple, and in many ways elegant solution to the problem of providing cost-effective, high-bandwidth,...
6728839 Attribute based memory pre-fetching technique  
An enhanced prefetching technique enables control of internal activities of a cache memory by a processor without relying on conventional algorithms. The cache memory is contained within a...
6694412 Multiprocessor digital data processing system  
A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies...
6681341 Processor isolation method for integrated multi-processor systems  
A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data...
6662252 Group and virtual locking mechanism for inter processor synchronization  
A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1)...
EP0606299B1 METHOD AND APPARATUS FOR CONCURRENT PACKET BUS  
Abstract not available for EP0606299 Abstract of corresponding document: WO9307569 A method and apparatus for transmitting data between nodes (10) connected to a communications bus (14),...
6567837 Object oriented processor arrays  
An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. The object...
6529983 Group and virtual locking mechanism for inter processor synchronization  
A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the...
6513108 Programmable processing engine for efficiently processing transient data  
A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as...
6505269 Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system  
A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique...
6456594 Multi-protocol communications routing optimization  
A communications switching system employing multi-protocol routing optimization which utilizes predetermined and measured parameters in accordance with a set of user priorities in determining the...
6442669 Architecture for a process complex of an arrayed pipelined processing engine  
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing...
6385747 Testing of replicated components of electronic device  
A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test...
6356548 Pooled receive and transmit queues to access a shared bus in a multi-port switch asic  
A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic...
6332185 Method and apparatus for paging data and attributes including an atomic attribute for digital data processor  
A digital data processing apparatus has a primary data storage element that stores data for access by one or more processes, as well as a secondary data storage element, e.g., a disk drive, for...
6272621 Synchronization and control system for an arrayed processing engine  
A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine...
6253372 Determining a communication schedule between processors  
To generate an optimum communication schedule when data is transmitted or received between processors which constitute a parallel computer or a distributed multiprocessor system. Processors which...
6195739 Method and apparatus for passing data among processor complex stages of a pipelined processing engine  
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing...
6173386 Parallel processor with debug capability  
A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and...
EP1061695A2 Method and apparatus for maintaining packet order integrity in a parallel switching engine  
A method and apparatus for maintaining packet order integrity in a switching engine wherein inbound packets are forwarded to different ones of parallel processing elements for switching. Order...
6148034 Apparatus and method for determining video encoding motion compensation vectors  
An MPEG-1 or an MPEG-2 motion compensation vector encoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry, including ROMs, designed to implement residue arithmetic...
EP0601029B1 MASSIVELY PARALLEL COMPUTER SYSTEM INCLUDING INPUT/OUTPUT ARRANGEMENT  
Abstract not available for EP0601029 Abstract of corresponding document: WO9304438 A computer comprising a plurality of processing elements (11) and an input/output processor (13) interconnected...
6119215 Synchronization and control system for an arrayed processing engine  
A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine...
6101599 System for context switching between processing elements in a pipeline of processing elements  
A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core...
6094715 SIMD/MIMD processing synchronization  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
6088758 Method and apparatus for distributing data in a digital data processor with distributed memory  
A digital data processing system and method with shared, distributed memory transfers data between corresponding data sets within memory. The digital data processing system includes a plurality of...
6076131 Routing resource reserve/release protocol for multi-processor computer systems  
A method and apparatus for reserving and releasing routing paths in a parallel processing computer system. The present invention eliminates the need to restart the computer system to recover from a...
6044080 Scalable parallel packet router  
A scalable parallel packet router comprises a massively parallel computer 10 and a plurality of multiplexers 15, and is controlled by a disclosed packet routing algorithm, and a method of very...
5966528 SIMD/MIMD array processor with vector processing  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5963746 Fully distributed processing memory element  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5963745 APAP I/O programmable router  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory...
5963212 Parallel computing system for modeling and data processing  
A parallel computing system useful for volume visualization, numeric, symbol, and other computing applications. The parallel computing system includes a memory storage system indexed to provide a...
5914953 Network message routing using routing table information and supplemental enable information for deadlock prevention  
A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements....
5913070 Inter-connector for use with a partitionable massively parallel processing system  
Apparatus is described for allocating the resources of a parallel computer. The computer is divided into a plurality of processor arrays, a plurality of host computers are provided, and the host...
5878241 Partitioning of processing elements in a SIMD/MIMD array processor  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5867723 Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface  
An advanced massively parallel computer having a plurality of processor subsystems, where each processor subsystem is coupled to a secondary storage device (e.g., disk drive) through a secondary...
5842031 Advanced parallel array processor (APAP)  
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a...
5828894 Array processor having grouping of SIMD pickets  
Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate...
5822608 Associative parallel processing system  
Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip...
Matches 1 - 50 out of 183 1 2 3 4 >