Matches 1 - 29 out of 29
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EP0518527B1 Method of reducing wasted bus bandwidth in a computer system  
Abstract of EP0518527 In a multiprocessor computer system (10), wasted bus bandwidth resulting from slow responding slaves (S) is reduced by relinquishing the master (M) that was busied by the...
5481753 I/O device having identification register and data register where identification register indicates output from the data register to be an identifier or normal data  
To enable data transfer between desired clock synchronous serial input/output devices without the need of a specific transmission/reception protocol, ordinary data and device number data for...
5463658 Low impact collision detection method  
A bus driver circuit having an active low-side driver and a hybrid high-side driver. When driving a logic high, the bus driver circuit delivers an active "kick" to pull the bus to a logic high...
5428797 Circuitry for eliminating bus contention at high frequencies by driving a bus to an available state prior to its relinquishing control of the bus  
Apparatus for switching data to a bus including apparatus for driving a bus to a first data receiving condition during a first clock period, apparatus for driving the bus to a second data awaiting...
5287463 Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions  
An atomic ordered sequence of information phase transitions allows for the design of a pure hardware protocol controller for use in a small storage interconnect bus. The information phase...
EP0518527A2 Method of reducing wasted bus bandwidth in a computer system.  
In a multiprocessor computer system (10), wasted bus bandwidth resulting from slow responding slaves (S) is reduced by relinquishing the master (M) that was busied by the slow responding slave, and...
5165024 Information transfer and receiving system with a ring interconnect architecture using voucher and ticket signals  
A computer system interconnection including a plurality of nodes each such node being associated with at least one of a plurality of computer system components. Transmission apparatus connects each...
5150467 Method and apparatus for suspending and restarting a bus cycle  
In a system which includes a processor which executes bus cycles on a bus and in which a signal is sent back to the processor indicative of completion of a bus cycle, completion of the cycle is...
5077787 Data communication apparatus  
A data communication apparatus can reserve at least transmissions of first data and second data, and can effect transmission data of the second data before the completion of transmission of the...
5077662 Microprocessor control system having expanded interrupt capabilities  
To expand the interrupt capabilities of a microprocessor system without restructing system architecture, intermediate levels of priority are created for a given interrupt request. Plural interrupts...
5019966 Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data  
A transmitting data processor comprises a data processing unit for supplying a predetermined length of data to be transferred and generating a transfer start signal, and a data transferring unit...
4947478 Switching control system for multipersonality computer system  
An interprocessor link system has a plurality of processor units having a common input/output device. The system further has at least one flip-flop for setting a processor mode so as to switch...
4908749 System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal  
A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy...
4858173 Apparatus and method for responding to an aborted signal exchange between subsystems in a data processing system  
In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus...
4835769 Passive bus communication for ISDN  
An apparatus for providing passive bus communication in an ISDN without use of services of a central office includes a passive bus suitable for ISDN D-channel frame communication, the passive bus...
4807109 High speed synchronous/asynchronous local bus and data transfer method  
A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting...
4787033 Arbitration mechanism for assigning control of a communications path in a digital computer system  
Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device...
4764862 Resilient bus system  
A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus...
4763243 Resilient bus system  
A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus...
4745546 Column shorted and full array shorted functional plane for use in a modular array processor and method for using same  
A column shorted and full array shorted functional plane for simultaneously transferring, or shorting, data to and from the data exchange subsystems of the array processor. This functional plane...
4706190 Retry mechanism for releasing control of a communications path in digital computer system  
When a device on a computer communications bus receives a request to enter into a transaction and is not yet ready to perform the transaction, it sends a retry signal to the requesting device to...
4641237 Bus control method and apparatus  
A bus control method and apparatus wherein buses each coupling a pair of processors are serially arranged rectilinearly into a cluster bus which is arranged in one direction and wherein a plurality...
4613936 Centralized generation of data transfer acknowledge pulses for microprocessors  
Centralized generation of data transfer acknowledgment (DTACK) pulses is provided instead of providing each of the devices with their own DTACK pulse generation facilities. In this centralized...
4609995 Priority controller  
A priority controller includes a pair of read only memories and a register. The register stores information identifying a request circuit to which priority has recently been granted. Corresponding...
4602327 Bus master capable of relinquishing bus on request and retrying bus cycle  
A bus master is provided with the capability to accept a data transfer task from a CPU, which includes the performance of a predetermined sequence of data transfer operations between memory and a...
4543642 Data Exchange Subsystem for use in a modular array processor  
A Data Exchange Subsystem comprising a data bus for transferring data signals, a load for normally maintaining a logical one signal on the data bus, a number of data receivers operatively connected...
4516205 Access control of data transmission network  
A system for controlling access to a data transmission network of a bus configuration. After a communication unit has completed transmission of a message block, the communication unit transmits a...
4516204 Optical passive bus control system  
An optical passive bus control system includes an access coordinator and control unit which is connected to the passive network in the same manner as other connected devices of the network. The...
EP0138676A2 Retry mechanism for releasing control of a communications path in a digital computer system.  
A retry mechanism facilitates release of a communications path by a device which is either unable to respond to a requested operation or which is unable to do so within a reasonable length of time....
Matches 1 - 29 out of 29