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7386689 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal...
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7197686 |
Reconfigurable bit-manipulation node
A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the...
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6912626 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal...
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6578133 |
MIMD array of single bit processors for processing logic equations in strict sequential order
A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The...
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6477281 |
Image processing system having multiple processors for performing parallel image data processing
An image processing apparatus is composed of an image memory comprising a plurality of memory elements, and a processor unit comprising a plurality of processor elements. By suitably engineering...
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6263494 |
Data updating method using overlap area and program converting device for converting update program in distributed-memory parallel processor
In a parallel processor, a local area and an overlap area are assigned to the memory of each processing element (PE), and each PE makes calculations to update the data in both areas at the runtime....
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6108763 |
Simultaneous parity generating/reading circuit for massively parallel processing systems
A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements for carrying data messages between the processing...
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6094715 |
SIMD/MIMD processing synchronization
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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6079008 |
Multiple thread multiple data predictive coded parallel processing system and method
A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding...
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6073251 |
Fault-tolerant computer system with online recovery and reintegration of redundant components
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs...
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6067609 |
Pattern generation and shift plane operations for a mesh connected computer
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a...
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5966528 |
SIMD/MIMD array processor with vector processing
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5963746 |
Fully distributed processing memory element
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5963745 |
APAP I/O programmable router
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory...
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5913070 |
Inter-connector for use with a partitionable massively parallel processing system
Apparatus is described for allocating the resources of a parallel computer. The computer is divided into a plurality of processor arrays, a plurality of host computers are provided, and the host...
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5890003 |
Interrupts between asynchronously operating CPUs in fault tolerant computer system
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the...
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5878241 |
Partitioning of processing elements in a SIMD/MIMD array processor
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5842031 |
Advanced parallel array processor (APAP)
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a...
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5828894 |
Array processor having grouping of SIMD pickets
Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate...
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5826095 |
Method and apparatus for maintaining the order of data items processed by parallel processors
A data processing system includes two or more parallel processors, a distributor and a combiner. The processors process input data items and generate corresponding output data items. The...
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5822608 |
Associative parallel processing system
Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip...
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5815723 |
Picket autonomy on a SIMD machine
A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has...
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5809292 |
Floating point for simid array machine
A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein...
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5805915 |
SIMIMD array processing system
A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically...
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5794059 |
N-dimensional modified hypercube
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in...
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5784630 |
Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of...
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5765015 |
Slide network for an array processor
In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor...
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5765012 |
Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library
A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function,...
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5761523 |
Parallel processing system having asynchronous SIMD processing and data parallel coding
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5754871 |
Parallel processing system having asynchronous SIMD processing
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5752067 |
Fully scalable parallel processing system having asynchronous SIMD processing
Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5734921 |
Advanced parallel array processor computer package
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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EP0577813B1 |
DATABUS PARITY AND HIGH SPEED NORMALIZATION CIRCUIT FOR A MASSIVELY PARALLEL PROCESSING SYSTEM
Abstract not available for EP0577813 Abstract of corresponding document: WO9315460 A processing array including a plurality of processing elements; and an interconnection network connected to all...
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5729757 |
Super-computer system architectures using status memory to alter program
A computer system is disclosed in which instruction sequencing is under the control of a program control computer, but each individual instruction is assigned for execution to an individual...
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5717944 |
Autonomous SIMD/MIMD processor memory elements
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5717943 |
Advanced parallel array processor (APAP)
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a...
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5713037 |
Slide bus communication functions for SIMD/MIMD array processor
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5710935 |
Advanced parallel array processor (APAP)
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a...
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5708836 |
SIMD/MIMD inter-processor communication
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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EP0800133A1 |
Databus parity and high speed normalization circuit for a massively parallel processing system
A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements, wherein each of the processing elements includes a...
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5675736 |
Multi-node network with internode switching performed within processor nodes, each node separately processing data and control messages
A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages...
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5630162 |
Array processor dotted communication network based on H-DOTs
A parallel processor array of the SIMD or MIMD type requires a highly organized communication network for communication between processing elements (PEs). For a communication network a dotted...
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5625836 |
SIMD/MIMD processing memory element (PME)
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5617577 |
Advanced parallel array processor I/O connection
A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used...
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5613067 |
Method and apparatus for assuring that multiple messages in a multi-node network are assured fair access to an outgoing data stream
A multi-node data processing system implements a method that assures that plural messages are enabled "fair" access to a data stream. Each node includes apparatus for controlling message...
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5594918 |
Parallel computer system providing multi-ported intelligent memory
A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their...
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5588152 |
Advanced parallel processor including advanced support hardware
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
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5542074 |
Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an...
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5535408 |
Processor chip for parallel processing system
A monolithic processing chip for a parallel processing system comprises a processor circuit and a memory circuit. The processor circuit processes data received from said associated memory circuit...
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5530661 |
Data bit-slicing apparatus and method for computing convolutions
A computer architecture that can rapidly perform a variety of repetitive mathematical operations on multimedia data sets comprises a data processing engine having n data processing devices, each of...
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