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7410873 |
Method of manufacturing a semiconductor device
A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert...
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7369436 |
Vertical NAND flash memory device
Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
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7339239 |
Vertical NROM NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
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7332773 |
Vertical device 4F2 EEPROM memory
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
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7282762 |
4F2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
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7241654 |
Vertical NROM NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
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7157771 |
Vertical device 4F2 EEPROM memory
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments...
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7148538 |
Vertical NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings,...
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7095075 |
Apparatus and method for split transistor memory having improved endurance
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device...
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7075146 |
4F2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of...
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7015525 |
Folded bit line DRAM with vertical ultra thin body transistors
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
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6995057 |
Folded bit line DRAM with vertical ultra thin body transistors
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
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6903367 |
Programmable memory address and decode circuits with vertical body transistors
Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar...
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6894532 |
Programmable logic arrays with ultra thin body transistors
Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane...
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6890812 |
Method of forming a memory having a vertical transistor
Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar...
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6881627 |
Flash memory with ultra thin vertical body transistors
Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating...
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