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US20070204222 |
Method and Apparatus for Rendering Content on a Browser
In one embodiment, the invention provides a method, comprising: receiving user-defined settings to control the rendering of content by a browser; receiving content from a web-server, the content...
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US20070204221 |
Order independent batched updates on a text buffer
The embodiments contemplate a system and method for the application of concurrent edits to the same version of a text. The concurrent edits may occur simultaneously or near simultaneously through...
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US20070204220 |
RE-LAYOUT OF NETWORK CONTENT
Techniques for modifying network content layout to be presented by an application are disclosed. More specifically, the content layout or portions thereof can be altered to facilitate specific...
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US20070204219 |
Method, system, and computer program product for propagating remotely configurable posters of host site content
A method, system, and computer program product for propagating access to host site content to remote users over the World Wide Web are provided. Access to host site content is distributed more...
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US20070204218 |
User-defined private maps
A method, device, and system for presenting one or more user-defined private maps with a public map for sharing among a group of users are disclosed. The device includes a processor for executing...
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US20070204217 |
Exporting a document in multiple formats
Systems and methods are disclosed for exporting a document in multiple formats. The disclosed systems and methods may include creating a metafile including content associated with the document and...
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US20070204216 |
System and method for creating layouts using a layout editor
A system, method, and program product are provided that receives a plurality of layout configuration selections from a user editing a layout configuration is provided. The layout configuration...
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US20070204215 |
Device for analyzing log files generated by process automation tools
A log file analysis device includes a partition of log file data generated by a process automation tool into a hierarchy of process data structures, a corresponding display object created for each...
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US20070204214 |
XML payload specification for modeling EDI schemas
Modeling an electronic data interchange (EDI) document using extensible Markup Language (XML) at runtime. A plurality of structural elements is identified in the EDI document. A plurality of...
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US20070204213 |
FORM MULTIPLEXER FOR A PORTAL ENVIRONMENT
A method to manage inputs from multiple portlets of a portal page may include gathering any inputs from forms associated with portlets other than a form associated with a portlet that is being...
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US20070204212 |
Dynamic thresholds for conditional formats
Generally described, embodiments of the present invention provide the ability to utilize dynamic thresholds and dynamic threshold values when generating variable formatting rules to be applied to a...
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US20070204211 |
Apparatus and method for creating literary macrames
By the use of program scripts, databases, and other software elements, taking as input a set of text files making up a work of literature of substantial size, converting the files to an...
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US20070204210 |
Standardized network access to partial document imagery
A method, apparatus and article of manufacture for network access of partial document imagery is described. In one embodiment, the method comprises receiving a request for a region of a page of a...
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US20070204209 |
Combining and displaying multimedia content
A method and system to manage rendering of multimedia content are provided. A theme specifies a collection of layouts defining multimedia content placement. The multimedia content is processed to...
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US20070204208 |
DEVICE AND METHOD FOR CORRECTING KINESCOPE SCAN DISTORTION
We describe a device and an associated method that includes an EHT signal processing module to generate a compensated gain signal responsive to a first EHT signal. A field fly-back processing...
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US20070204207 |
Error correction code decoder
An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome...
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US20070204206 |
Electronic Data Flash Card with Reed Solomon Error Detection and Correction Capability
One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being...
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US20070204205 |
Method and system for application of unequal error protection to uncompressed video for transmission over wireless channels
A method and system of wireless communication is provided which involves inputting information bits, wherein certain bits have higher importance level than other bits, and applying unequal...
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US20070204204 |
Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features
Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through...
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US20070204203 |
Layered multiple description coding
A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description...
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US20070204202 |
INFORMATION RECORDING DISC, RECORDING AND/OR REPRODUCING DEVICE AND METHOD
Four ECC blocks are recorded in a burst cutting area of an optical disc. Each ECC block is constituted by a BCA content code of 1 byte, content data length of 1 byte, and content data of 14 bytes....
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US20070204201 |
HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with...
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US20070204200 |
HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with...
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US20070204199 |
Semiconductor memory device and memory system including the same
A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory...
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US20070204198 |
Apparatus and method for transmitting/receiving signal in communication system
Disclosed is an apparatus and a method for transmitting/receiving a signal in a communication system, which generates an Affine Permutation Matrix-Low Density Parity Check (APM-LDPC) codeword by...
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US20070204197 |
Decoding device, control method, and program
A decoding device for decoding LDPC (Low Density Parity Check) codes includes a message calculation unit for performing a variable node calculation for decoding the LPDC codes using a message to be...
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US20070204196 |
STREAMING AND BUFFERING USING VARIABLE FEC OVERHEAD AND PROTECTION PERIODS
Data is streamed from a transmitter to a receiver, wherein streaming is transferring data with an assumption that the receiver will begin using the data before it is all transmitted and received...
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US20070204195 |
APPARATUS AND METHOD FOR TRACKING PACKETS IN A RELIABLY CONNECTED TRANSMISSION SYSTEM
A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates...
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US20070204194 |
TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator...
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US20070204193 |
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical...
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US20070204192 |
METHOD FOR DETECTING DEFECTS OF A CHIP
A method for detecting a defect of a chip includes: utilizing a plurality of scan patterns to scan a plurality of scan chains of the chip; for each of the scan patterns, obtaining a suspected...
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US20070204191 |
METHOD FOR DETECTING A MALFUNCTION IN A STATE MACHINE
A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine...
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US20070204190 |
Test algorithm selection in memory built-in self test controller
An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry...
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US20070204189 |
Method and system for testing a random access memory (RAM) device having an internal cache
A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising:...
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US20070204188 |
ERROR CORRECTION METHOD AND REPRODUCTION APPARATUS
A reproduction method includes a step of performing error correction of the first coded data piece and generating error location information which represents an error location of the first coded...
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US20070204187 |
METHOD, SYSTEM AND STORAGE MEDIUM FOR A MULTI USE WATER RESISTANT OR WATERPROOF RECORDING AND COMMUNICATIONS DEVICE
A method, system and storage medium for a multi-use water resistant or waterproof recording and communications device. A network system of embodiments herein comprises an information engine to...
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US20070204186 |
Processor with flexible clock configuaration
A network processor or other type of processor includes clock generation circuitry which generates one or more clock signals for each of a number of clock domains of the processor. The clock...
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US20070204185 |
Data fetch circuit and control method thereof
To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a...
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US20070204184 |
DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A...
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US20070204183 |
Method and apparatus for processing abnormal conditions of a backup-type power supply system
A method and an apparatus to process abnormal conditions of a backup-type power supply system aims to provide duty loading values to allow the backup-type power supply system to independently...
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US20070204182 |
Data terminal device
A cellular phone in the form of a shell downloads and reproduces encrypted content data distributed from a distribution server. The cellular phone includes a detection unit detecting whether its...
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US20070204181 |
Information processing apparatus and power consumption method
According to one embodiment, there is provided an information processing apparatus including a control portion to change the operation mode to the first power consumption mode when a remaining...
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US20070204180 |
Method for power management of central processing unit and system thereof
A method for power management of CPU and a system thereof which drive the CPU enter a most efficient power saving state is disclosed. A chip of the present invention sends a first control signal to...
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US20070204179 |
Minimize Energy Consumption Using Optimal Voltage Assignment Algorithm
Low energy consumptions are extremely important in real-time embedded systems. Due to the uncertainties in execution time of some tasks, this paper models each varied execution time as a...
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US20070204178 |
Power supply selection/detection circuit
A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power...
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US20070204177 |
Power controller coupling assemblies and methods
A variety of power controller coupling assemblies are provided that include at least one power controller, at least one cable assembly coupled to the power controller, and a plurality of power...
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US20070204176 |
Apparatus and Method for Centralized Power Management
The invention describes a system and method for arranging to provide power to a power monitor device. The disclosure describes the system and method receiving a request for power for at least one...
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US20070204175 |
Processing system and methods for use therewith
A processing system includes a processing module and a memory module for storing plurality of data. A controllable power source supplies a source voltage to the memory module in response to a...
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US20070204174 |
Power management in a portable media delivery system
A consumer electronic product that includes a media player arranged to process a selected one of a plurality of digital media files stored therein and a media delivery accessory unit detachedly...
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US20070204173 |
CENTRAL PROCESSING UNIT AND ENCRYPTED PIN PAD FOR AUTOMATED TELLER MACHINES
A system and method for securing a central processing unit and/or encrypting pin pad (EPP) for an automated teller machine from tampering is disclosed. A user input is provided that has a plurality...
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