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US20080104484 Mass storage system and method  
There is provided a system and method of mass storage. The method includes dividing storage units into standard sized blocks and upon receiving a write request from an application, generating EDC...
US20080104483 Error corrector with a high use efficiency of a memory  
An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory...
US20080104482 Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors  
Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of...
US20080104481 Encoding device, decoding device, encoding/decoding device and recording/reproducing device magnetic head and method of producing the same  
An encoding/decoding device corrects errors by concatenated codes of an ECC code and a parity code to prevent an increase in the circuit scale and to improve error correction performance. The...
US20080104480 METHOD FOR PROCESSING NOISE INTERFERENCE  
A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum...
US20080104479 Symbol Error Correction by Error Detection and Logic Based Symbol Reconstruction  
Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more...
US20080104478 Method and system for providing a contention-free interleaver for channel coding  
A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, {right arrow over (v)},...
US20080104477 Method for performing error corrections of digital information codified as a symbol sequence  
A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to...
US20080104476 METHOD, SYSTEM, AND APPARATUS FOR ADJACENT-SYMBOL ERROR CORRECTION AND DETECTION CODE  
A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases.
US20080104475 METHOD AND APPARATUS FOR ENCODING AND DECODING HIGH SPEED SHARED CONTROL CHANNEL  
A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive...
US20080104474 Low Density Parity Check (Ldpc) Decoder  
A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter...
US20080104473 Rendering and correcting data  
Rendering and correcting data. Data is received. The data is stored at a memory. The data is rendered for presentation at an output device. Defects in the data stored at the memory are determined....
US20080104472 Parameter setting with error correction for analog circuits  
A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from...
US20080104471 Method and apparatus for testing an IC device based on relative timing of test signals  
An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for...
US20080104470 Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test  
A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test,...
US20080104469 Apparatus and Method for Using a Single Bank of eFuses to Successively Store Testing Data from Multiple Stages of Testing  
An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy...
US20080104468 Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures  
A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault...
US20080104467 TIMING FAILURE REMEDYING APPARATUS FOR AN INTEGRATED CIRCUIT, TIMING FAILURE DIAGNOSING APPARATUS FOR AN INTEGRATED CIRCUIT, TIMING FAILURE DIAGNOSING METHOD FOR AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT, COMPUTER READABLE RECORDING MEDIUM RECORDED THEREON A TIMING FAILURE DIAGNOSING PROGRAM FOR AN INTEGRATED CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM RECORDED THEREON A TIMING FAILURE REMEDYING PROGRAM FOR AN INTEGRATED CIRCUIT  
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core...
US20080104466 Method and Apparatus for Testing Embedded Cores  
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
US20080104465 FAILURE SIMULATION BASED ON SYSTEM LEVEL BOUNDARY SCAN ARCHITECTURE  
A method and apparatus for reducing cost for the backplane and system test and for speeding up the time to market of a new product is disclosed. A failure simulation based on system level Boundary...
US20080104464 Method and Apparatus for Controlling Access to and/or Exit From a Portion of Scan Chain  
The present invention provides a method, apparatus and program product for providing controlled access to and/or exit from a portion of a scan chain. The method, apparatus, and program product take...
US20080104463 METHOD AND SYSTEM FOR TESTING CHIPS  
Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then...
US20080104462 Serializer/de-serializer bus controller inferface  
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core...
US20080104461 ATE architecture and method for DFT oriented testing  
An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes...
US20080104460 Medium defect detector and information reproducing device  
A reproducing device performs error correction, detects a medium defect at an early stage and performs erasure correction. A reproducing device having an error correction circuit is provided with a...
US20080104459 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE  
A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold...
US20080104458 Semiconductor memory, system, testing method for system  
A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and...
US20080104457 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DISPLAY CONTROLLER  
The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device...
US20080104456 Memory system including asymmetric high-speed differential memory interconnect  
A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a...
US20080104455 Software failure analysis method and system  
A software failure analysis method for use following detection of a software failure on a computing system. The method includes collecting local data from the computing system pertaining to the...
US20080104454 System and method of error reporting in a video distribution network  
Method, systems and devices for error reporting in a video distribution network are disclosed. A method may include determining that a network communication error has occurred in a video...
US20080104453 System and Method to Detect Errors and Predict Potential Failures  
A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault...
US20080104452 Providing Policy-Based Application Services to an Application Running on a Computing System  
Methods, apparatus, products are disclosed for providing policy-based application services to an application running on a computing system. The computing system includes at least one compute node....
US20080104451 BOOTABLE POST CRASH ANALYSIS ENVIRONMENT  
A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the...
US20080104450 COMPUTER SYSTEM AND CONTROL METHOD THEREOF  
A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the...
US20080104449 Discrete device testing  
One embodiment in accordance with the invention is a method that comprises testing a first number of physical devices using a first test sequence that comprises an item. A second number of physical...
US20080104448 Testing apparatus for semiconductor device  
A testing apparatus for semiconductor device comprises test controllers 10 - 1, 10 - 2, . . . , 10 -N, variable clock generators 24 - 1, 24 - 2, . . . , 24 -N which are provided respectively...
US20080104447 DIAGNOSTIC REPAIR SYSTEM AND METHOD FOR COMPUTING SYSTEMS  
A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic...
US20080104446 HARD DISK DRIVE DATA SCRUB METHODOLOGY  
Method, system and computer program product for reporting and recovering from uncorrectable data errors in a data processing system using the Advanced Technology Attachment (ATA) or the Serial ATA...
US20080104445 RAID ARRAY  
A method of providing a RAID array, comprising providing an array of disks ( 202 a - 202 f ), creating an array layout ( 200 ) comprising a plurality of blocks (D 1 -D 26, P 1 -P 10 ) on each of...
US20080104444 System including a plurality of data storage devices connected via network and data storage device used therefor  
Embodiments of the present invention help improve the process for updating parities accompanied by the writing process. According to one embodiment, a host controller transmits a write command and...
US20080104443 INFORMATION SYSTEM, DATA TRANSFER METHOD AND DATA PROTECTION METHOD  
Availability of an information system including a storage system that performs remote copy between two or more storage apparatuses and a host computer using such storage system is improved. A third...
US20080104442 METHOD, DEVICE AND SYSTEM FOR AUTOMATIC DEVICE FAILURE RECOVERY  
Embodiments of the present invention provide a method, devices and a system for automatic device failure recovery. The method mainly includes: sending a recovery request message to a management...
US20080104441 DATA PROCESSING SYSTEM AND METHOD  
A method of kernel panic recovery, comprising detecting a kernel panic of a first kernel, retrieving at least some of a state of at least one thread running on the first kernel, and restoring the...
US20080104440 SYSTEM AND METHOD FOR TOD-CLOCK STEERING  
A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to...
US20080104439 REAL TIME CLOCK HAVING A REGISTER  
In a real time clock having a register, a preinstalled central processing unit issues a control instruction to hold a time stamp of an external register in the real time clock and then reads the...
US20080104438 Microcomputer, program and on-vehicle electronic controller  
A microcomputer is put into a sleep mode immediately when tasks become ready for the sleep mode so as to eliminate wasted power. Multiple application tasks are executed. Each application task...
US20080104437 COMPUTER SYSTEM AND CONTROL METHOD THEREOF  
A computer system. The computer system includes memory units; a power supply to supply power to the memory units; and a controller to controls the supply of power the plurality of memory units so...
US20080104436 Computer device power management system and method  
A computer device power management system comprises a controller configured to throttle a processor of a computer device responsive to an overcurrent condition associated with a power source...
US20080104435 Clock Generator, Timing and Frequency Reference with Crystal-Compatible Power Management  
Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock...