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US20080098299 |
Document conversion and use system
A document conversion and use system which converts a first structured document into a second structured document different in structure from the first structured document, comprising: a template...
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US20080098298 |
Compound Web Document Generation Method and Web-based Editing System for Generating a Compound Web Document
Files of various file formats are converted into markup language files, such as HTML files or XML-based files, and a compound web document is generated from the markup language files so that the...
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US20080098297 |
METHOD AND SYSTEM FOR PROVIDING PRESENCE INFORMATION
The present invention discloses a method for providing presence information, including: setting a validity period of the presence information; publishing, by a presentity client, the received...
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US20080098296 |
Rendering hypertext markup language content
In general, one aspect of the subject matter described in this specification can be embodied in a method that includes rendering Hyper Text Markup Language (HTML) content, in an HTML rendering...
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US20080098295 |
Annotation Management System
An annotation management system for providing real-time annotations for media content during a videoconference session is provided. The annotation management system includes a media management...
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US20080098294 |
COLLABORATIVE ANNOTATION OF ELECTRONIC CONTENT
An apparatus, program product and method provide a collaborative annotation environment that permits viewers of electronic content to share their personal annotations with other viewers of the...
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US20080098293 |
METHOD AND SYSTEM FOR STYLESHEET EXECUTION INTERACTIVE FEEDBACK
A method (and structure) for displaying mapping relationships defined by a plurality of instruction elements, each instruction element providing a relation between zero or more source elements and...
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US20080098292 |
Automatic document reader and form population system and method
A system, and method for automatic population of a form with data from an identification document. The system has a computer and an identification document reader or card scanner coupled to the...
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US20080098291 |
Method and System for Cross-Platform Form Creation and Deployment
The present invention is directed to systems and methods of creating and deploying electronic forms for collecting information from a user using a browser, where the browser may be one of a...
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US20080098290 |
METHOD AND SYSTEM FOR PROVIDING A WIDGET FOR DISPLAYING MULTIMEDIA CONTENT
A system and computer implemented method for providing a widget are described. The method and system include receiving a rule and at least one condition corresponding to the rule for the widget....
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US20080098289 |
METHOD AND SYSTEM FOR PROVIDING A WIDGET FOR DISPLAYING MULTIMEDIA CONTENT
A system and computer implemented method for providing a widget for dynamically displaying multimedia content are described. The method and system include receiving a plurality of parameters for an...
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US20080098288 |
FORWARD DECISION AIDED NONLINEAR VITERBI DETECTOR
A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least...
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US20080098287 |
Detection and mitigation of temporary impairments in a communications channel
Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the...
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US20080098286 |
Irregular Systematic with Serial Concatenated Parity Codes
Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of...
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US20080098285 |
APPARATUS FOR RANDOM PARITY CHECK AND CORRECTION WITH BCH CODE
An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The...
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US20080098284 |
SYSTEMS, METHODS, APPARATUS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING FORWARD ERROR CORRECTION WITH LOW LATENCY
Systems, methods, apparatus and computer program products for providing forward error correction with low latency to live streams in networks are provided, including outputting source data at a...
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US20080098283 |
OUTER CODING METHODS FOR BROADCAST/MULTICAST CONTENT AND RELATED APPARATUS
Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by techniques that occur when the User Equipment (UE) moves...
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US20080098282 |
HIGH SPEED ERROR CORRECTING SYSTEM
Disclosed is an error correcting system, which comprises: a demodulator, for receiving and demodulating data from the optical disc to generate input data; a data buffer, for storing the input data;...
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US20080098281 |
USING SAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS
SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation...
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US20080098280 |
N-dimensional iterative ECC method and apparatus with combined erasure - error information and re-read
In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error...
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US20080098279 |
USING NO-REFRESH DRAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS
Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many...
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US20080098278 |
Multiplier product generation based on encoded data from addressable location
For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number,...
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US20080098277 |
HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS
A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and...
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US20080098276 |
SEMICONDUCTOR INTEGRATED CIRCUIT
The present invention provides a data transmission method capable of suppressing degradation in data rate while improving a bit error rate of transmission data, and transmitters and receivers...
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US20080098275 |
SYSTEM AND PROGRAM PRODUCT FOR ERROR RECOVERY WHILE DECODING CACHED COMPRESSED DATA
A system and program for decoding cached compressed data. Compressed data is received and decoded. An error is detected while decoding a first location in the compressed data. A reentry data set is...
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US20080098274 |
DATA TRANSMISSION APPARATUS AND METHOD
Provided are a data transmission apparatus and method which apply an appropriate coding rate according to significance of bits or bit groups included in uncompressed data and retransmit all or part...
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US20080098273 |
METHOD AND APPARATUS FOR ENCODING AND DECODING DATA
A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block...
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US20080098272 |
Networked test system
An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using...
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US20080098271 |
System and Method for Verification and Generation of Timing Exceptions
The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second...
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US20080098270 |
Method For Determining Time to Failure of Submicron Metal Interconnects
The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such...
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US20080098269 |
Mechanism for concurrent testing of multiple embedded arrays
In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to...
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US20080098268 |
USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT ISOLATION AND DIAGNOSTIC DATA COLLECTION
In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified....
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US20080098267 |
Semiconductor IC and testing method thereof
According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum...
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US20080098266 |
REDUCED SIGNALING INTERFACE METHOD AND APPARATUS
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the...
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US20080098265 |
System and Method for Embedded Java Memory Footprint Performance Improvement
A system and method are provided to allow demand loading and discarding of Java executable image (JXE) files. The virtual machine allocates an address space for a requested JXE program. The...
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US20080098264 |
PROGRAM DEBUG METHOD AND APPARATUS
The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation...
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US20080098263 |
Test apparatus and method for testing booting and shutdown process of computer system
A test apparatus for testing a booting and shutdown process of a computer system provided. The test apparatus includes a power control unit and a test control unit. The power control unit is for...
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US20080098262 |
Performing diagnostic operations upon an asymmetric multiprocessor apparatus
An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10 . A master diagnostic...
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US20080098261 |
ADAPTIVE RECOVERY FROM SYSTEM FAILURE FOR APPLICATION INSTANCES THAT GOVERN MESSAGE TRANSACTIONS
Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory...
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US20080098260 |
Methods and apparatus for handling processing errors in a multi-processing system
Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a...
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US20080098259 |
METHOD, SYSTEM, AND PROGRAM FOR ERROR HANDLING IN A DUAL ADAPTOR SYSTEM WHERE ONE ADAPTOR IS A MASTER
Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is...
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US20080098258 |
METHOD, SYSTEM, AND PROGRAM FOR ERROR HANDLING IN A DUAL ADAPTOR SYSTEM WHERE ONE ADAPTOR IS A MASTER
Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is...
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US20080098257 |
Multiple Execution-Path System
A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a...
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US20080098256 |
COMPUTER READABLE STORAGE MEDIUM FOR MIGRATABLE SERVICES
A migration framework provides for the migration of services in a cluster. A migratable target contains a list of servers in the cluster capable of hosting a migratable service. A migration manager...
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US20080098255 |
COMMUNICATION MANAGEMENT APPARATUS AND COMMUNICATION MANAGEMENT METHOD
A transmitting/receiving unit receives a SIP signal after occurrence of trouble in a SIP server and outputs a call ID of the SIP signal to a recovery-file searching unit. A session control unit...
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US20080098254 |
Method for Autonomous Dynamic Voltage and Frequency Scaling of Microprocessors
A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their...
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US20080098253 |
Method of timing calibration using slower data rate pattern
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than...
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US20080098252 |
Computation of processor clock frequency ratios
An embodiment of the invention provides an apparatus for computation of processor clock frequency ratios in a multi-processor system. The apparatus includes a computation engine configured to...
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US20080098251 |
DIGITAL DATA BUFFER
A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a...
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US20080098250 |
Power supply management system, terminal, information processor, power supply management method and computer readable medium
The power supply management system is provided with an information processor and a terminal that is connected to the information processor by a communication line and a power supply line and that...
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