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US20080059700 |
PORTABLE STORAGE DEVICE CAPABLE OF TRANSFERRING DATA TO A PORTABLE STORAGE DEVICE
Embodiments of the present invention relate to a device includes both a transferring and receiving interface. The device may include a direction indicator, for example an arrow, indicating a...
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US20080059699 |
SYSTEM AND METHOD OF MIRRORED RAID ARRAY WRITE MANAGEMENT
The write operations to the storage devices are managed so that the write operations that would force a storage device to reposition its read/write head outside its read optimization boundary are...
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US20080059698 |
Method for Automatic RAID Configuration on Data Storage Media
A method of configuring a virtual disk for an information handling system is disclosed. The method comprises embedding a data structure onto a data storage medium prior to installing the medium...
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US20080059697 |
Storage system and control method for the same
An object of the present invention is to integrally manage disk storage apparatuses through virtualization. Some physical storage apparatuses 14 connected to a host computer 10 via a...
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US20080059696 |
SYSTEM AND METHOD FOR COMPARAND REUSE
An invention is provided for using a comparand provided to a CAM for multiple CAM operations without requiring the comparand to be reloaded from a host processor for each CAM operation. The...
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US20080059695 |
METHOD FOR CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY SYSTEM
In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply...
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US20080059694 |
HYBRID HARD DISK DRIVE AND DATA STORAGE METHOD THEREOF
A hybrid hard disk drive includes a hard disk drive controller to receive a plurality of write commands from a host, a buffer to receive and store write data, which are input through the hard disk...
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US20080059693 |
METHOD FOR IMPROVING LIFESPAN OF FLASH MEMORY
A method for improving the lifespan of flash memory is provided. By defining and configuring a plurality of memory block counters, the method assigns a counter to each memory block to record the...
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US20080059692 |
Device for prioritized erasure of flash memory
A storage device having prioritized-erasure capabilities including: a memory for storing data, the memory having at least one flash unit, wherein each flash unit has a plurality of blocks; and a...
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US20080059691 |
Memory management module
A methodology for efficiently copying data is presented. An internal controller RAM is multiplexed between an existing RAM data and a copy back operation RAM. The data in the controller RAM is...
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US20080059690 |
Self-updating memory controller
A system and method of making a firmware self updatable depending on option information stored in a configuration module. The configuration module can either be in a memory device or a memory...
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US20080059689 |
DATA STORAGE APPARATUS THAT APPROPRIATELY REVISES FDCB INFORMATION DURING BACKGROUND FORMATTING
A data storage apparatus, including a controller that formats a rewritable recording medium in the background, interrupts the background formatting when a host computer requests to store data in...
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US20080059688 |
Crossbar control circuit
A control circuit includes a crossbar array having input columns and output rows configured to store first stored data in the form of high or low resistance states. The input columns are connected...
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US20080059687 |
SYSTEM AND METHOD OF CONNECTING A PROCESSING UNIT WITH A MEMORY UNIT
A method and system comprising at least two processing units that are connected with at least two memory units, wherein first data buses are connected with the memory units, wherein second data...
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US20080059686 |
Multiple context single logic virtual host channel adapter supporting multiple transport protocols
Various embodiments provide methods and systems operable to receive a work queue pair from one of a plurality of host nodes, to scan the work queue pair for known data formats corresponding to one...
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US20080059685 |
MOTHERBOARD
A motherboard includes a chipset, a first connector pad suitable for receiving a first type of PCI connector, a second connector pad suitable for receiving a second type of PCI connector, a...
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US20080059684 |
APPARATUS FOR COORDINATING INTEROPERABILITY BETWEEN DEVICES OF VARYING CAPABILITIES IN A NETWORK
Embodiments of a routing device for coordinating the interoperability of devices with varying capabilities that send and/or receive commands in a storage network are disclosed. A host device in the...
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US20080059683 |
Method and Apparatus for Conditional Broadcast of Barrier Operations
A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A...
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US20080059682 |
METHOD TO EMBED PROTOCOL FOR SYSTEM MANAGEMENT BUS IMPLEMENTATION
A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method including embedding a component address having...
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US20080059681 |
PORT REPLICATING APPARATUS
A docking assembly including a port replicating apparatus is disclosed. The docking assembly includes a port replicating apparatus including (i) a housing having a major dimension defined by a...
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US20080059680 |
Single Chip Universal Serial Bus (USB) Package with Metal Housing
A Universal Serial Bus (USB) memory card includes a tube metal housing that is rectangularly-shaped and a Chip-On-Board (COB)-Universal Serial Bus (USB) device and a carrier substrate having a...
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US20080059679 |
APPLICATION PROCESSOR CIRCUIT INCORPORATING BOTH SD HOST AND SLAVE FUNCTIONS AND ELECTRONIC DEVICE INCLUDING SAME
An application processor circuit has SD-compatible interface protocols and can perform both host and slave functions. The circuit includes SD bus interface logic for realizing SD interface signals...
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US20080059678 |
Half-sized PCI central processing unit card and computer device having the capability of PCIe expansion
This invention is to provide a half-sized PCI CPU card and a computer device having the capability of PCIe expansion, wherein the half-sized PCI CPU card comprises a PCI golden finger and a PCIe...
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US20080059677 |
FAST INTERRUPT DISABLING AND PROCESSING IN A PARALLEL COMPUTING ENVIRONMENT
Embodiments of the present invention provide techniques for protecting critical sections of code being executed in a lightweight kernel environment suited for use on a compute node of a parallel...
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US20080059676 |
EFFICIENT DEFERRED INTERRUPT HANDLING IN A PARALLEL COMPUTING ENVIRONMENT
Embodiments of the present invention provide techniques for protecting critical sections of code being executed in a lightweight kernel environment suited for use on a compute node of a parallel...
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US20080059675 |
Method and apparatus for arbitrating access
When four access request origins A, B, C, and D are present, a priority table (No. 1 ) having a priority order of A, B, C, and D, a priority table (No. 2 ) having a priority order of B, D, A, and...
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US20080059674 |
Apparatus and method for chained arbitration of a plurality of inputs
An apparatus for chained arbitration of a plurality of inputs for access to a shared resource is provided. The apparatus includes a plurality of levels of arbiters including a first arbitration...
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US20080059673 |
System and Method for Measuring Latch Contention
A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available...
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US20080059672 |
Methods and Apparatus for Scheduling Prioritized Commands on a Bus
In a first aspect, a first method of scheduling a command to be issued on a bus is provided. The first method includes the steps of (1) associating an address and priority with each of a plurality...
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US20080059671 |
Data transfer method in a daisy chain arrangement
The present invention relates to a method for the serial transmission of data items comprising at least one start identifier and subsequent user data in a daisy chain arrangement having at least...
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US20080059670 |
CONTROL METHOD AND SYSTEM OF CONSTRUCTING RAID CONFIGURATION ACROSS MULTIPLE HOST BUS ADAPTERS
A control method of constructing a RAID configuration across multiple host bus adapters in a data-processing system includes the following steps. Firstly, a master host bus adapter and at least a...
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US20080059669 |
Method and Apparatus for Enhancing Data Rate of Advanced Micro-Controller Bus Architecture
A method for enhancing data rate of an advanced micro-controller bus architecture (AMBA) having an AHB system and an APB system includes simultaneously receiving control signals outputted from a...
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US20080059668 |
MULTIPLE COMMUNICATION CHANNELS ON MMC OR SD CMD LINE
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced...
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US20080059667 |
Two-Cycle Return Path Clocking
Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may...
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US20080059666 |
MICROCONTROLLER AND DEBUGGING METHOD
A microcontroller has a RAM monitor function that facilitates debugging by enabling a debugging device to specify a location and access the specified location during program execution. Access takes...
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US20080059665 |
Systems and methods of inter-frame compression
A system and method for rendering images, and performing operations such as windowing and leveling, when the parameters of a client appliance are known and rendering images when the parameters of a...
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US20080059664 |
METHOD AND SYSTEM FOR PROVIDING AND CONTROLLING SUB-BURST DATA TRANSFERS
The present apparatus and method control the flow of communication between a host and a data storage device. A plurality of data transport streams are maintained as active while a first burst of...
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US20080059663 |
Methods and Appartus for Providing Data Transfer Control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
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US20080059662 |
Program initiation control apparatus
A CPU reads a system initialization program from a first recording area and stores the read system initialization program to an internal memory, and then reads the system initialization program...
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US20080059661 |
USB COMMUNICATION SYSTEM, USB DEVICE, AND METHOD OF ERROR DETECTION FOR USB COMMUNICATION SYSTEM
A USB communication system, a USB device, and a method of error detection for the USB communication system; with which an error of any breaking of physical connection in USB communication can be...
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US20080059660 |
PORTABLE DATA STORAGE DEVICE
A portable data storage device ( 10 ) includes a universal serial bus (USB) coupling device ( 1 ) and an interface device ( 2 ) is coupled to the USB coupling device ( 1 ). The portable data...
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US20080059659 |
Wireless IC memory, accessing apparatus for use of wireless IC memory, accessing control method for use of wireless IC memory, and wireless IC memory system
A wireless IC memory, for improving the security thereof, for achieving protection of business information and privacy, comprises an RFID tag 100 , wherein it is possible to setup “readout...
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US20080059658 |
Controlling the feeding of data from a feed buffer
*A method includes feeding data from a feed buffer to an interface, receiving at least one signal dependent on a temperature external to the interface, determining from the at least one received...
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US20080059657 |
System and Method for Pushing Information from a Host System to a Mobile Data Communication Device
A scheme for pushing user data items from a messaging host system in real-time delivery to a wireless mobile data device that is associated with a computer connected over a network to the messaging...
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US20080059656 |
Content synchronization among associated computing devices
Methods, apparatuses, and articles for synchronizing contents of associated computing devices are described herein. In various embodiments, the method includes receiving, by a first computing...
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US20080059655 |
COORDINATED TIMING NETWORK CONFIGURATION PARAMETER UPDATE PROCEDURE
In a networked data processing system, the updating of timing parameters is carried out via a process in which the detection of the loss of communications with the network is not immediately...
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US20080059654 |
Object oriented communication among platform independent systems over networks using SOAP
A system for object oriented communication among platform independent systems over networks using SOAP, in which communications can be performed over the internet utilizing a single communications...
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US20080059653 |
Method and system for active profile server
A system and method for active profile services is provided. An embodiment includes an active profile server that is configured to respond to requests for subscriber profile information from an...
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US20080059652 |
Routing for Detection of Servers Within a Communication Network
The invention relates to network equipment (R 2 ) comprising: means for communicating with neighbouring devices which are connected by means of communication networks; and routing means for...
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US20080059651 |
Distribution of XML documents/messages to XML appliances/routers
XML appliances/routers may be organized to implement one or more XML distribution rings to enable XML documents/messages to be distributed efficiently. The rings may be logical or physical. The XML...
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