Match Document Document Title
US20160049986 DEVICE FOR TRANSMITTING AND RECEIVING CARRIER AGGREGATION SIGNAL  
Disclosed is a signal transmit and receive device capable of receiving and processing both a carrier-aggregated (CA) receive signal and a non-CA receive signal, and transmitting both a CA transmit...
US20160049985 SWITCHABLE RF TRANSMIT/RECEIVE MULTIPLEXER  
A switchable RF transmit/receive (TX/RX) multiplexer, which includes a group of RF TX bandpass filters, a group of RF TX switching elements, and a group of RF RX bandpass filters; is disclosed....
US20160049984 WIRELESS TRANSCEIVER WITH TX/FBRX SEQUENTIAL QMC CALIBRATION USING SEPARATE/SHARED PLLS  
A direct conversion wireless transceiver is configured for TX/FBRX sequential QMC calibration (coefficient generation) using separate/shared PLLs. A TX path includes a TX LO driving upconversion,...
US20160049983 APPARATUS FOR HOLDING A MOBILE COMMUNICATION DEVICE  
An apparatus for holding a mobile communication device, comprising at least one finger-receiving and engaging structure fixable to a mobile communication device. The finger-receiving and engaging...
US20160049982 MULTIFUNCTION BACK COVER FOR CELL PHONE  
A multifunction back cover for cell phone is disclosed. The back cover is installed on a cell phone body having at least one application mode. An entity button and an electric quantity indicator...
US20160049981 PROTECTION DEVICE CAPABLE OF ROTATABLY SUPPORTING A PORTABLE ELECTRONIC DEVICE  
A protection device for rotatably supporting a portable electronic device includes a cover, a holder and a transmission cable. The holder has a first surface and a second surface opposite to each...
US20160049980 Phone Case  
A protecting case is provided for a mobile electronic device, including a front edge frame, a rear edge frame, and a front cover. The front edge frame comprises an inner groove portion, an outer...
US20160049979 Nogo - Protective cover with front camera cover for mobile devices  
The present invention discloses a protective device for a mobile device (smart phone or tablet), comprising: a frame comprising a first sidewall, a second sidewall opposite to the first sidewall,...
US20160049978 Specific Absorption Rate Mitigation  
Specific Absorption Rate (SAR) mitigation techniques are described herein. In one or more embodiments, a host device is configured to implement a SAR mitigation algorithm to maintain compliance...
US20160049977 CARD SOCKET DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME  
Disclosed are a card socket device and an electronic apparatus including the same. The card socket device includes a seat portion configured to receive an attachable card; and one or more...
US20160049976 Managing Transmitter Collisions  
Various embodiments implemented on a mobile communication device (e.g., a multi-SIM-multi-active communication device) mitigate degraded transmit performance typically experienced by a...
US20160049975 ENABLING PRE-PROVISIONED PROPRIETARY CARRIER-SPECIFIC FEATURE SERVICES AND APPLICATIONS FOR EXECUTION ON A MOBILE DEVICE  
A pre-provisioned mobile device and a system are provided that enables selection of proprietary feature services and proprietary applications specific to one cellular carrier from among two or...
US20160049974 Systems and Methods for Parallel Signal Cancellation  
A receiver includes a first finger that receives a non-interference-cancelled signal and output first demodulated data, a first phase estimate, and a first PN code. The receiver also includes a...
US20160049973 Phase-Noise Cancellation Apparatus and Method  
A noise cancellation method comprises receiving, by an adaptive phase-noise cancellation apparatus, a noise-corrupted symbol from a receiver, performing a hard decision process on the...
US20160049972 Interference Cancellation in MIMO Same Channel Full-duplex Transceivers  
Same-channel full-duplex communications can be adapted for multiple-input multiple-output (MIMO) processing in order to derive increased signal performance through the exploitation of spatial...
US20160049971 IMPULSE NOISE MITIGATION UNDER OUT-OF-BAND INTERFERENCE CONDITIONS  
An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters...
US20160049970 RADIO COMMUNICATION DEVICES AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE  
A radio communication device is described comprising: a receiver configured to receive radio signals on a radio channel; a noise level determination circuit configured to determine a noise level...
US20160049969 COMPENSATION FOR A SIGNAL DAMPING WHILE TRANSMITTING TRANSMISSION SIGNALS OF A WIRELESS MOBILE DEVICE  
A circuit arrangement compensates for signal damping while transmitting transmission signals of a wireless mobile device. The circuit arrangement contains an adjustable signal level amplifying...
US20160049968 Method and Apparatus for Controlling Interference in Mobile Communication System  
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as a...
US20160049967 RF TRANSMITTER FOR ELECTRICALLY SHORT ANTENNA  
An RF transmitter comprises a capacitive energy storage, an output stage and a switching circuit with an open state and a closed state. The capacitive energy storage forms with the antenna when...
US20160049966 RFIC ARCHITECTURE FOR MULTI-STREAM REMOTE RADIO HEAD APPLICATION  
One embodiment of the present invention provides a remote radio head (RRH) for a wireless communication system. The RRH includes a first integrated circuit (IC) chip that comprises multiple...
US20160049965 TUNABLE RF TRANSMIT/RECEIVE MULTIPLEXER  
A tunable RF transmit/receive (TX/RX) multiplexer, which includes a tunable RF TX/RX diplexing circuit and a first group of RF RX bandpass filters, is disclosed. The tunable RF TX/RX diplexing...
US20160049964 NOVEL FORWARD ERROR CORRECTION ARCHITECTURE AND IMPLEMENTATION FOR POWER/SPACE EFFICIENT TRANSMISSION SYSTEMS  
A concatenated Forward Error Correction (FEC) code method, at an intermediate point, includes receiving, from an ingress point, a signal that is fully encoded with a concatenated FEC code, wherein...
US20160049963 CONVOLUTIONAL DEINTERLEAVER  
A receiver (103) is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions (403)...
US20160049962 METHOD AND APPARATUS OF LDPC ENCODER IN 10GBASE-T SYSTEM  
A method of data encoding is disclosed. A communications device receives a set of information bits to be encoded into a codeword (c), which includes the set of information bits and a set of parity...
US20160049961 ENCODING METHOD, DECODING METHOD  
An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first...
US20160049960 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD  
In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding...
US20160049959 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049958 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049957 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049956 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049955 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049954 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049953 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049952 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME  
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory...
US20160049951 HARDWARE COMPRESSION TO FIND BACKWARD REFERENCES WITH MULTI-LEVEL HASHES  
Concurrently writing an uncompressed data element, if the uncompressed data element comprises an indication that it is valid, in a main hash table using a first address generated by a first hash...
US20160049950 DEFEAT OF ALIASING BY INCREMENTAL SAMPLING  
A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method...
US20160049949 N-Path Interleaving Analog-to-Digital Converter (ADC) with Offset gain and Timing Mismatch Calibration  
A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved...
US20160049948 MULTI-ZONE DATA CONVERTERS  
Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized...
US20160049947 SPREAD SPECTRUM CLOCK GENERATOR  
A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase...
US20160049946 ALL DIGITAL PHASE LOCKED LOOP WITH CONFIGURABLE MULTIPLIER HAVING A SELECTABLE BIT SIZE  
An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase...
US20160049945 COMPENSATING FOR HYSTERETIC CHARACTERISTICS OF CRYSTAL OSCILLATORS  
In some examples, compensating for hysteretic characteristics of a crystal oscillator in a timing circuit includes obtaining a plurality of successive temperature measurements. From the plurality...
US20160049944 SEMICONDUCTOR DEVICE, MEASUREMENT DEVICE, AND CORRECTION METHOD  
A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral...
US20160049943 SEMICONDUCTOR DEVICE AND METERING APPARATUS  
A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency...
US20160049942 PROGRAMMABLE INTERCONNECTION DEVICE  
The invention relates to a programmable interconnection device, comprising: first rows of functional blocks, each functional block having inputs and outputs; second rows of programmable...
US20160049941 PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS  
Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires,...
US20160049940 INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT  
An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to...
US20160049939 Switch Driver Circuit And Associated Methods  
A driver circuit for driving a switch includes a high output impedance driver circuit portion having a high impedance output node coupled to the control terminal of the transistor and a low output...
US20160049938 SEMICONDUCTOR DEVICE  
A semiconductor device includes a first block coupled between a first latch node and a second latch node, a second block suitable for generating common-mode noise between the first latch node and...
US20160049937 ACTIVITY CORRELATION BASED OPTIMAL CLUSTERING FOR CLOCK GATING FOR ULTRA-LOW POWER VLSI  
A clustering bus-specific clock gating method is described to reduce the dynamic power consumed by redundant clock ticks in gate-level. The method exploits correlations between flip-flops for...