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US20070005905 |
Prefetching apparatus, prefetching method and prefetching program product
The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a...
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US20070005904 |
Read ahead method for data retrieval and computer system
Execution of the read-ahead function to fragmented data will result only in caching non-contiguous physical blocks, failing to hit and wasting any read-ahead data. Even if file accesses are...
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US20070005903 |
System and method for dynamic data prefetching
According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination...
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US20070005902 |
INTEGRATED SRAM CACHE FOR A MEMORY MODULE AND METHOD THEREFOR
A memory module having at least one random access memory device and a memory bus on a substrate. The memory module further comprises an SRAM cache interfaced with the random access memory device...
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US20070005901 |
Adaptive input / output compressed system and data cache and system using same
To improve caching techniques, so as to realize greater hit rates within available memory, of the present invention utilizes a entropy signature from the compressed data blocks to supply a bias to...
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US20070005900 |
Cache flushing
Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second...
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US20070005899 |
Processing multicore evictions in a CMP multiprocessor
A method and apparatus for improving snooping performance is disclosed. One embodiment provides mechanisms for processing multi-core evictions in a multi-core inclusive shared cache processor. By...
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US20070005898 |
Method, apparatus and system for task context cache replacement
A device includes a cache memory having a locked segment and an unlocked segment. A controller is connected to the cache memory. A method partitions a cache memory into context segments and...
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US20070005897 |
Intergrated circuit and a method of cache remapping
An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted...
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US20070005896 |
Hardware oriented host-side native command queuing tag management
Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit...
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US20070005895 |
Cache memory device and microprocessor
A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache...
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US20070005894 |
Computer system having logically ordered cache management
A computer system is set forth that includes a processor, general memory storage, and cache memory for temporarily storing selected data requested from the general memory storage. The computer...
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US20070005893 |
Correlated logic micro cache
A correlated logic micro cache and approach for correlated logic micro-caching. For one aspect, logic coupled to an output node is provided to at least initiate computation of an output value in...
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US20070005892 |
Identifying relevant data to cache
The present invention extends to methods, systems, and computer program products for identifying relevant information to cache. A computer system accesses a marked data entity that has been marked...
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US20070005891 |
Fast hit override
In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag...
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US20070005890 |
Automatic detection of micro-tile enabled memory
In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory...
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US20070005889 |
Method, device, and system to avoid flushing the contents of a cache by not inserting data from large requests
A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write...
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US20070005888 |
Wide-port context cache apparatus, systems, and methods
Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of...
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US20070005887 |
Caching resources requested by applications
Provided are a method, system, and program for caching resources requested by applications. Resources requested by applications are cached, wherein the applications use the resources to access...
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US20070005886 |
Disk array apparatus and control method for disk array apparatus
Resources of a storage apparatus are utilized effectively by increasing and reducing a capacity of a differential LU used in a snapshot. In a disk array apparatus including a control processor...
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US20070005885 |
RAID apparatus, and communication-connection monitoring method and program
An interdevice communication monitoring unit 62 - 1 calculates a variable timeout time (T 2 −T) by subtracting an elapsed time T from a predetermined fixed timeout time T 2 for monitoring an...
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US20070005884 |
Disk drive and method of controlling cache memory therein
A processing speed is improved when there is a pattern in which read requests making access to continuous areas in an LBA space repeatedly alternate with write requests making access to continuous...
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US20070005883 |
Method to keep volatile disk caches warm across reboots
In some embodiments, a method to keep volatile disk caches warm across reboots is presented. In this regard, a caching agent is introduced to, responsive to a system boot, load a cache data from a...
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US20070005882 |
System and method for scheduling disk writes in an application server or transactional environment
A system and a method for scheduling disk writes for use with an application server, transactional system, or other server. The disk scheduler and method is independent of the underlying operating...
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US20070005881 |
Minimizing memory bandwidth usage in optimal disk transfers
In some embodiments, a method to minimize memory bandwidth usage in optimal disk transfers is presented. In this regard, a transfer agent is introduced to read a plurality of contiguous sections of...
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US20070005880 |
Techniques for providing communications in a data storage system using a single IC for both storage device communications and peer-to-peer communications
An improved data storage system has a set of storage devices, a first storage processor and a second storage processor for storing data into and retrieving data from the set of storage devices. The...
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US20070005879 |
Data update system, data update device and external storage medium
When update data stored in portable storage media are distributed to update data, the data updatable frequency can be freely restricted at the distribution source of the update data. A data...
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US20070005878 |
CAM modified to be used for statistic calculation in network switches and routers
A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM...
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US20070005877 |
System and method to increase DRAM parallelism
A method and apparatus for a multi-ranked memory protocol. In some embodiments an apparatus may include a memory controller (MC), and a plurality of ranked dynamic random access memory (DRAM)...
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US20070005876 |
Semiconductor storage device
Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a...
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US20070005875 |
Memory card using flash memory and method of controlling the same
There is disclosed a memory having a plurality of blocks including management information, and a centralized management block in which the management information of each block is centralized,...
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US20070005874 |
File system storing transaction records in flash-like media
A computer system having a transaction based file system is set forth. The computer system includes a processor, a persistent data storage device that is accessible by the processor, and file...
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US20070005873 |
ECU identification retention across reprogramming events
A memory system for a vehicle includes a first memory that is non-volatile, that is rewritable, and that stores a control program and identification data. A second memory is non-volatile. A control...
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US20070005872 |
Information processing apparatus and method of controlling the same
An information processing apparatus including a memory device which sets, in a case where the information processing apparatus transmits the packet to the slave device, and receive the packet...
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US20070005871 |
Using a block device interface to invoke device controller functionality
A standard block device command is received at a device controller, the standard block device command addressed to a virtual block device associated with the device controller, the standard block...
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US20070005870 |
Virtualizing memory type
A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization...
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US20070005869 |
Index/data register pair for indirect register access
A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are...
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US20070005868 |
Method, apparatus and system for posted write buffer for memory with unidirectional full duplex interface
In some embodiments, a method, apparatus and system for posted write buffer for memory with unidirectional full duplex interface are presented. In this regard, a buffer agent is introduced to send...
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US20070005867 |
Virtual peripheral device interface and protocol for use in peripheral device redirection communication
A virtual peripheral device interface and protocol are described that may be used in redirecting peripheral device communication to a remote networked device. In on embodiment, the invention...
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US20070005866 |
System and method for managing the sharing of PCI devices across multiple host operating systems
A system and method is disclosed for initializing PCI devices in a computer system or information handling system. Upon initialization of the system, each operating system instance of the system...
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US20070005865 |
Enforcing global ordering using an inter-queue ordering mechanism
An arrangement is provided for efficiently enforcing global ordering in a computing system using an inter-queue ordering mechanism (IQOM). The IQOM may be located in a bridge (e.g., a caching...
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US20070005864 |
Data transfer apparatus and data transfer method
A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. ...
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US20070005863 |
HOT-PLUGGABLE VIDEO DISPLAY CARD AND COMPUTER SYSTEM THEREOF
A hot-pluggable video display card and a computer system thereof are provided. The video display card includes a hot-pluggable host-side interface, a video processing unit, and a...
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US20070005862 |
Communications protocol expander
An expander device is configurable to identify itself as an end device and not an edge expander device. Other embodiments are also described and claimed.
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US20070005861 |
FAULT TOLERANT COMPUTER SYSTEM
A computing hardware and software device called a Meta Mentor Central Processing Unit. The Meta Mentor purpose is to control memory, input/output interfaces, defining the operating system, the...
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US20070005860 |
Interrupt control system and method
An interrupt control system is applied in an electronic device having an interrupt service system, for controlling the interrupt service system to execute corresponding interrupt handlers. The...
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US20070005859 |
Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications
In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and...
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US20070005858 |
Extended message signal interrupt
Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are...
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US20070005857 |
Bus system and method of arbitrating the same
A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB),...
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US20070005856 |
HDD controller and system equipped with the same
An HDD controller executes high-speed burst data transfer, at which the HDD controller has a master mode for the HDD controller to work as a bus master of a PCI bus, and a slave mode for the HDD...
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