Matches 351 - 400 out of 24586 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
US20080164579 PROCESS FOR CHEMICAL VAPOR DEPOSITION OF MATERIALS WITH VIA FILLING CAPABILITY AND STRUCTURE FORMED THEREBY  
A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is...
US20080164558 METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURES USING DIBLOCK COPOLYMER PATTERNING  
A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area...
US20080164540 METHOD AND APPARATUS FOR FORMING NICKEL SILICIDE WITH LOW DEFECT DENSITY IN FET DEVICES  
A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing...
US20080164532 EMBEDDED STRESSED NITRIDE LINERS FOR CMOS PERFORMANCE IMPROVEMENT  
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces...
US20080164528 SELF-ALIGNED METAL-SEMICONDUCTOR ALLOY AND METALLIZATION FOR SUB-LITHOGRAPHIC SOURCE AND DRAIN CONTACTS  
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned...
US20080164525 Structure and Method for Mosfet Gate Electrode Landing Pad  
A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair...
US20080164507 Area-Efficient Gated Diode Structure and Method of Forming Same  
An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper...
US20080164495 HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH SELF-ALIGNED SUB-LITHOGRAPHIC METAL-SEMICONDUCTOR ALLOY BASE CONTACTS  
A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the...
US20080164494 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR  
Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped...
US20080164493 Structures containing electrodeposited germanium and methods for their fabrication  
Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film,...
US20080164491 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE  
While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed...
US20080164455 Programmable Non-Volatile Resistance Switching Device  
A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical...
US20080164403 Wide Dynamic Range Sensor  
A sensor and method for widening a dynamic range of sensor circuitry for sensing energy, such as light energy. The sensor circuitry includes a sensor and recharge circuitry for sharing additional...
US20080164312 On-Demand Point-of-Sale Scanner Access  
Associating and/or disassociating a mobile point-of-sale scanner device with a particular shopper. Shoppers may be identified, for example, using biometrics or by scanning a loyalty card. As an...
US20080164059 METHOD AND SYSTEM OF FEEDING CABLE THROUGH AN ENCLOSURE WHILE MAINTAINING ELECTROGNETIC SHIELDING  
An exemplary embodiment disclosed herein relates to a method of feeding cable through a wall. The method includes, cutting an outer jacket of a cable, and pulling the outer jacket away from the cut...
US20080163631 METHODS FOR CONFIGURING TUBING FOR INTERCONNECTING IN-SERIES MULTIPLE LIQUID-COOLED COLD PLATES  
Methods of configuring a cooling subassembly for an electronics system are provided, that is, for establishing a coolant-carrying tube layout for interconnecting multiple liquid-cooled cold plates...
US20080163487 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES  
A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane....
US20080163382 METHOD AND SYSTEM FOR PROTECTING SENSITIVE DATA IN A PROGRAM  
To protect sensitive data in program code, a method includes providing a programming interface with a capability of allocating a protected region of memory which can only be accessed by authorized...
US20080163268 MESSAGE FORMATION AND DISTRIBUTION IN HETEROGENEOUS NETWORKS  
A system is disclosed for communicating with a plurality of network processors, one or more of the processors having a different operating environment, includes receiving an application programming...
US20080163264 Directory Service that Provides Information from a Plurality of Disparate Data Sources  
At least a first application program interface (API) may be provided to support retrieval of data from a plurality of disparate data sources. A directory from which data from at least one of the...
US20080163249 System for Workload Balancing by Resetting an Average Queue Depth upon the Start of the Server Instance  
The present invention relates to an apparatus and computer program for workload balancing in an asynchronous messaging system. The number of server instances, which process work items from a queue...
US20080163242 INFORMATION PROCESSING APPARATUS, METHOD, AND PROGRAM FOR CONTROLLING RESOURCE ACCESS BY APPLICATION PROGRAM  
A method executed in an information processing apparatus for controlling resource access by an application program running on the information processing apparatus is provided. A change in...
US20080163222 PARALLEL APPLY PROCESSING IN DATA REPLICATION WITH PRESERVATION OF TRANSACTION INTEGRITY AND SOURCE ORDERING OF DEPENDENT UPDATES  
A computer readable medium encoded with a computer program for handling transaction messages in asynchronous data replication in a database system is disclosed. The computer program provides a high...
US20080163213 METHOD AND A SYSTEM FOR COMPOSING AN OPTIMALLY-GRAINED SET OF SERVICE FUNCTIONS  
Disclosed is a computer program product for managing granularity of a computing infrastructure, wherein the program, when executed on a computer, causes the computer to: identify at least one set...
US20080163207 MOVEABLE ACCESS CONTROL LIST (ACL) MECHANISMS FOR HYPERVISORS AND VIRTUAL MACHINES AND VIRTUAL PORT FIREWALLS  
A method (and system) which provides virtual machine migration with filtered network connectivity and control of network security of a virtual machine by enforcing network security and routing at a...
US20080163206 VIRTUALIZING THE EXECUTION OF HOMOGENEOUS PARALLEL SYSTEMS ON HETEROGENEOUS MULTIPROCESSOR PLATFORMS  
A method of virtual processing includes running a virtual processor ( 1 ), which when the virtual processor ( 1 ) encounters a faulting instruction unmaps the virtual processor ( 1 ) from the...
US20080163196 APPARATUS AND METHOD FOR AUTOMATICALLY DEFINING, DEPLOYING AND MANAGING HARDWARE AND SOFTWARE RESOURCES IN A LOGICALLY-PARTITIONED COMPUTER SYSTEM  
A partition wizard allows automatically defining from a set of system requirements a solution profile that defines a combination of hardware and software in multiple logical partitions to satisfy...
US20080163191 SYSTEM AND METHOD FOR FILE TRANSFER MANAGEMENT  
Through methods, systems and program codes, a file download URL is used to navigate to a download server, the download server downloading or not downloading a file to a party in response to the URL...
US20080163179 INHERITANCE BREAKPOINTS FOR USE IN DEBUGGING OBJECT-ORIENTED COMPUTER PROGRAMS  
An apparatus and program product utilize an inheritance breakpoint to assist in debugging an object-oriented computer program having a method identified in a base class or interface and implemented...
US20080163176 Using Memory Tracking Data to Inform a Memory Map Tool  
A method of runtime analysis for a computer program can include generating runtime data relating to memory usage for an instrumented computer program and creating a memory map comprising a...
US20080163175 LOCK SUITABILITY ANALYSIS SYSTEM AND METHOD  
A method and computer program product for detecting an attempt to engage a synchronization object. A tracking list for a line of code that attempted to engage the synchronization object is updated.
US20080163164 SYSTEM AND METHOD FOR MODEL-DRIVEN DASHBOARD FOR BUSINESS PERFORMANCE MANAGEMENT  
A system, method, and framework resulting therefrom, for a model-driven dashboard for business performance management, which includes capturing business dashboard model requirements at a business...
US20080163163 MINIMIZING INTERACTION COSTS AMONG COMPONENTS OF COMPUTER PROGRAMS  
A method for minimizing total cost of interaction among components of a computer program, each of the components being characterized by at least one implementation property includes steps of: a)...
US20080163153 VERIFYING MASK LAYOUT PRINTABILITY USING SIMULATION WITH ADJUSTABLE ACCURACY  
A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the...
US20080163149 System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential  
A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual...
US20080163147 METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR STATIC TIMING WITH RUN-TIME REDUCTION  
Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing...
US20080163102 OBJECT SELECTION IN WEB PAGE AUTHORING  
Tag selection in web page authoring is facilitated without losing the advantages of WYSIWYG editing. A reference point for object selection is set in response to a user action performed on an...
US20080163074 IMAGE-BASED INSTANT MESSAGING SYSTEM FOR PROVIDING EXPRESSIONS OF EMOTIONS  
Emotions can be expressed in the user interface for an instant messaging system based on the content of a received text message. The received text message is analyzed using a text-to-speech engine...
US20080163052 METHOD AND SYSTEM FOR MULTI-MODAL FUSION OF PHYSICAL AND VIRTUAL INFORMATION CHANNELS  
A method and system for multi-modal fusion of physical and virtual information channels is provided. The method and system include a virtual information channel and physical information channel....
US20080163040 UBIQUITOUS VISITED LINKS  
Where a user logs on to a web page server, the server can maintain a history of links to web pages hosted by the server to indicate which links are visited by the user. In consequence, a user may...
US20080163032 SYSTEMS AND METHODS FOR ERROR DETECTION IN A MEMORY SYSTEM  
A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential...
US20080163016 SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA  
A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide...
US20080162998 AUTOMATIC RECONFIGURATION OF AN I/O BUS TO CORRECT FOR AN ERROR BIT  
A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus ( 0 to M−1). The test pattern is also generated at the receiver chip...
US20080162995 IN-CYCLE SYSTEM TEST ADAPTATION  
Disclosed are an information processing system and computer readable medium for performing a system test on a program. A test plan associated with a system test is created. The system test is for...
US20080162991 SYSTEMS AND METHODS FOR IMPROVING SERVICEABILITY OF A MEMORY SYSTEM  
Systems and methods for improving serviceability of a memory system including a method for identifying a failing memory element in a memory system when two or more modules operate in unison in...
US20080162946 METHOD AND SYSTEM FOR CONTENT-BASED ENCRYPTED ACCESS TO A DATABASE  
Some aspects of the invention provide methods, systems, and computer program products for inserting an encrypted problem signature into a symptom database. A problem signature is first provided,...
US20080162913 FAILOVER OF COMPUTING DEVICES ASSIGNED TO STORAGE-AREA NETWORK (SAN) STORAGE VOLUMES  
In response to determining that a computing device to which one or more storage volumes within a storage-area network (SAN) have been assigned has satisfied a shutdown criterion, the storage...
US20080162909 COMPILATION AND RUNTIME INFORMATION GENERATION AND OPTIMIZATION  
To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a...
US20080162898 REGISTER MAP UNIT SUPPORTING MAPPING OF MULTIPLE REGISTER SPECIFIER CLASSES  
Embodiments of this invention relate to sharing resources on a semiconductor between multiple functional units to reduce the number of register rename mappers and particularly to providing a way to...
US20080162897 Binary Logic Unit and Method to Operate a Binary Logic Unit  
A binary logic unit to apply any Boolean operation on two input signals (v a , v b ) is described, wherein any Boolean operation to be applied on the input signals (v a , v b ) is defined by a...
Matches 351 - 400 out of 24586 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >