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7146489 Methods for intelligent caching in an embedded DRAM-DSP architecture  
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and...
7146488 System and method for expanding processor functionality  
A system comprises at least one processor, and supporting firmware for supporting at least one function of the at least one processor. The system further comprises logic operable to expand the...
7146487 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution  
General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition...
7146486 SIMD processor with scalar arithmetic logic units  
A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different...
7146485 Rebuilding of dynamic maps and data managed thereby  
A mechanism is provided for storing self-defining data and mapping elements with either a fixed set of allowed structures or types or with the structures and types determined by rules. Recovery is...
7146484 Method and apparatus for caching storage system  
A caching storage method and system that includes one or more host devices, network devices, storage devices, and logical volume management functions. An input/output (I/O) request is received from...
7146483 Memory system  
A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a...
7146482 Memory mapped input/output emulation  
A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address...
7146481 Methods and systems for pre-merge read of configuration data from a foreign volume group inserted in storage array  
Methods and structure for storing volume and other configuration information on all disk drives of a volume group and for performing pre-merge operations to inform a user of the pending...
7146480 Configurable memory system  
A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality...
7146479 Method and apparatus of storage allocation/de-allocation in object-oriented programming environment  
Methods and/or systems and/or apparatus for improved memory management include different allocation and deallocation strategies for various sizes of objects needing memory allocation during runtime.
7146478 Cache entry selection method and apparatus  
A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises...
7146477 Mechanism for selectively blocking peripheral device accesses to system memory  
A system is configured to selectively block peripheral accesses to system memory. The system includes a secure execution mode (SEM)-capable processor configured to operate in a trusted execution...
7146476 Emulated storage system  
A method comprising acts of creating a full back-up data set comprising a first plurality of data files, creating at least one incremental back-up data set comprising a second plurality of data...
7146475 Data set level mirroring to accomplish a volume merge/migrate in a digital data storage system  
Users of Mainframe computers running under IBM's MVS operating systems have a need to merge migrate data from multiple smaller DASD devices (disk volumes) to larger DASD devices, and/or to migrate...
7146474 System, method and computer program product to automatically select target volumes for a fast copy to optimize performance and availability  
A computer-implemented method includes, in response to detecting that a fast copy function has been invoked, automatically selecting at least one target volume for writing fast copy-related data,...
7146473 Mechanism for ring buffering in an arbitrary-action tracing framework  
A method for storing a data set having an enabled probe identification component and an associated data component in a buffer, including storing the data set at a current offset if the buffer has...
7146472 Method for modification of data on a memory card on a transaction  
A method for modification of data in a card transaction system having a memory card and a reader for reading the card. The card has a first memory (RAM) and a second memory (EEPROM) with data...
7146471 System and method for variable array architecture for memories  
A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment...
7146470 Real-time motor controller with additional down-up-loadable controller functionality  
A controller, in particular a drive controller, includes a first functional block for at least one permanently installed controller function and a second functional block for at least one...
7146469 Method, apparatus, and system for improving memory access speed  
According to one embodiment of the invention, an apparatus comprises a high speed memory unit, a memory controller and an external bus interface (EBIF) unit coupled to the memory controller. The...
7146468 Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache  
A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query...
7146467 Method of adaptive read cache pre-fetching to increase host read throughput  
Exemplary systems, methods, and devices employ receiving an operational parameter characteristic of a storage device, and adapting a read cache pre-fetch depth based in part on the operational...
7146466 System for balancing multiple memory buffer sizes and method therefor  
A system for balancing multiple memory buffer sizes includes a memory partitioned into a plurality of subgroups, each subgroup containing similarly sized buffers. The system further includes a...
7146465 Determining maximum drive capacity for RAID-5 allocation in a virtualized storage pool  
Methods of determining the maximum storage capacity in a storage system that implements RAID-5 redundancy are described. In one implementation the method comprises determining a chunk size of...
7146464 Storage system  
A disk array includes a drive management unit, which is a program for identifying kinds of disk devices and managing different disk devices separately, and a drive management table for storing...
7146463 Methods and structure for optimizing disk space utilization  
Methods and associated structure to improve disk capacity utilization in the context of size coercion and COD space reservation techniques applied in a storage system. One aspect hereof provides...
7146462 Storage management method  
A computer system includes a host computer, a disk control device controlling operation of a storage sub-system, and a management server managing configuration of the storage sub-system. The host...
7146461 Automated recovery from data corruption of data volumes in parity RAID storage systems  
The present invention relates to an apparatus or computer executable method of detecting corrupt data in a RAID data storage system before the corrupted data is provided to a computer system...
7146460 Dynamic spindle usage leveling  
Methods of data leveling in a virtualized storage system are described. In one implementation, the method comprises detecting an event that changes the eligible storage capacity of a storage...
7146459 Writing a sequence of M bytes to a disk with continuous write steps aligned on 8 byte boundaries  
A method of writing data to a disk, said method performing a write-modify-read for every partial 8 byte write, said method comprising: receiving a request for a sequence of L bytes; determining...
7146458 System for storing streaming information in a circular buffer by using padding block containing non-streaming information to fill a partition of the buffer  
One aspect of the present invention relates to an information appliance for handling streaming information for storage in a circular buffer having a plurality of partitions defined by boundaries....
7146457 Content addressable memory selectively addressable in a physical address mode and a virtual address mode  
Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a...
7146456 Memory device with a flexible reduced density option  
A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures...
7146455 System and method for optimized access to memory devices requiring block writing  
A method of optimized access of information in the memory subsystem of a computer system that requires the writing of information in blocks of continuous memory space is disclosed. The inventive...
7146454 Hiding refresh in 1T-SRAM architecture  
A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external...
7146453 Reducing ABENDS through the use of second-tier storage groups  
A method and computer that reduces ABENDs due to end of volume encounters of a job. The method provides an extend-to-new volume processing in response to such encounters. The method permits the...
7146452 Multi-port system and method for routing a data element within an interconnection fabric  
The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection...
7146451 PCI bridge and data transfer methods  
A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data...
7146450 Control and supervisory signal transmission system for changing a duty factor of a control signal  
A parent station output section changes a duty factor between a period in which a control data signal is at a level (high-potential low-level) lower than a power supply voltage Vx but higher than...
7146449 Bluetooth association with simple power connection  
A method and system for wirelessly coupling a computer with a peripheral device. The peripheral device is initially docked to a docking port in the computer. The computer then listens for...
7146448 Apparatus and method for adopting an orphan I/O port in a redundant storage controller  
A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two...
7146447 System for facilitating the replacement or insertion of devices in a computer system through the use of a graphical user interface  
A computer software system is disclosed for facilitating a user's replacement or insertion of devices in a computer server network system. The system allows a user to swap or add peripheral devices...
7146446 Multiple module computer system and method  
A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console...
7146445 Daughtercard-based system software and hardware functionality-defining mechanism  
A test apparatus for telecommunication equipment includes motherboard that executes a resident operation control mechanism, so that the test apparatus exhibits default hardware functionality....
7146444 Method and apparatus for prioritizing a high priority client  
A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are...
7146443 Instruction encoding method for single wire serial communications  
An instruction encoding method is provided for communication between devices. Before transmission, each opcode is multiplied by two. Each operand is multiplied by two and incremented by one....
7146442 Motherboard having a non-volatile memory which is reprogrammable through a video display port  
A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video...
7146441 SRAM bus architecture and interconnect to an FPGA  
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of...
7146440 DMA acknowledge signal for an IDE device  
A method for using a personal computer memory card international association (PCMCIA) controller to communicate with an Integrated Drive Electronics (IDE) drive which includes performing a transfer...
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