Title:
Semiconductor element
United States Patent D432505


Inventors:
Oba, Haruo (Tokyo, JP)
Kondo, Yoshio (Tokyo, JP)
Application Number:
29/115446
Publication Date:
10/24/2000
Filing Date:
12/15/1999
Assignee:
Sony Corporation (JP)
Primary Class:
Field of Search:
D13/182, D13/105, D13/107, D13/114, D13/117, 174/521, 361/579, 361/728, 361/736, 361/737, 361/742, 361/752, 361/802, 439/328, 439/377
View Patent Images:
US Patent References:
D401912Semiconductor deviceDecember, 1998Majumdar et al.D13/182
D386475Read/write device for IC built-in cardsNovember, 1997HiramatsuD13/182
D379350Expanded jacketted circuit cardMay, 1997KerklaanD13/182
D376133Jacketed circuit cardDecember, 1996KerklaanD13/182
D375941Top, front, rear, left and right sides of an enlarged jacketed circuit cardNovember, 1996KerklaanD13/182
D358806Socketed integrated circuit packageMay, 1995Siegel et al.D13/182
D317592Semiconductor elementJune, 1991YoshizawaD13/182



Other References:
Publication; "DR-350", Kyocera; Sep. 1997; CF-2MB and CF-4MB.
Publication; "PowerShot"; Digital Camera; Cannon; Mar. 1997.
Publication; "Picona", NEC; Mar. 1997; PC-FH045 and PC-FH155.
Primary Examiner:
VINSON, BRIAN N
Attorney, Agent or Firm:
Monica Millner (Rader,Fishman &Grauer P.L.L.C. 1233 20th Street, N.W. Suite 501, Washington, DC, 20036, US)
Claims:
1. The ornamental design for a semiconductor element, as shown and described.

Description:

FIG. 1 is a perspective view of a semiconductor element showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a left side elevational view thereof;

FIG. 4 is a front elevational view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof; and,

FIG. 7 is a rear elevational view thereof.