Semiconductor element
United States Patent D421597
US Patent References:
Semiconductor element
Yoshizawa - June, 1991 - D317592

Socketed integrated circuit package
Siegel et al. - May, 1995 - D358806

Top, front, rear, left and right sides of an enlarged jacketed circuit card
Kerklaan - November, 1996 - D375941

Jacketed circuit card
Kerklaan - December, 1996 - D376133

Expanded jacketted circuit card
Kerklaan - May, 1997 - D379350


Inventors:
Oba, Haruo (Tokyo, JP)
Hibino, Takuro (Tokyo, JP)
Kondo, Yoshio (Tokyo, JP)
Application Number:
D/086990
Publication Date:
03/14/2000
Filing Date:
04/24/1998
View Patent Images:
Assignee:
Sony Corporation (Tokyo, JP)
Primary Class:
Field of Search:
D13/182, D13/105, D13/107, D13/114, D13/117, 174/521, 361/679, 361/728, 361/736, 361/737, 361/742, 361/752, 361/802, 439/328, 439/377
US Patent References:
D386475Read/write device for IC built-in cardsNovember, 1997HiramatsuD13/182
D401912Semiconductor deviceDecember, 1998Majumdar et al.D13/182
Primary Examiner:
Vinson, Brian N.
Attorney, Agent or Firm:
Foley & Lardner
Claims:
1. The ornamental design for a semiconductor element, as shown and described.

Description:

FIG. 1 is a perspective view of a first embodiment of a semiconductor element showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a left side elevational view thereof;

FIG. 4 is a front elevational view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof; and,

FIG. 7 is a rear elevational view thereof.

FIG. 8 is a perspective view of a second embodiment of a semiconductor element showing our new design;

FIG. 9 is a top plan view thereof;

FIG. 10 is a left side elevational view thereof;

FIG. 11 is a front elevational view thereof;

FIG. 12 is a bottom plan view thereof;

FIG. 13 is a right side elevational view thereof; and,

FIG. 14 is a rear elevational view thereof.