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7617499 |
Context switch instruction prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of at least one instruction likely to be executed by a thread prior to resuming...
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7603673 |
Method and system for reducing context switch times
An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The apparatus...
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7603566 |
Authenticated process switching on a microprocessor
A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification...
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7600084 |
Register file with integrated routing to execution units for multi-threaded processors
A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.
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7596682 |
Architected register file system utilizes status and control registers to control read/write operations between threads
An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only...
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7594234 |
Adaptive spin-then-block mutual exclusion in multi-threaded processing
Adaptive modifications of spinning and blocking behavior in spin-then-block mutual exclusion include limiting spinning time to no more than the duration of a context switch. Also, the frequency of...
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7586492 |
Real-time display post-processing using programmable hardware
In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an...
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7584474 |
Systems and methods for transaction chaining
A transaction management engine, such as a business process management (BPM) engine, can allow an application to define transaction demarcations in order to ensure that portions of a workflow are...
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7583268 |
Graphics pipeline precise interrupt method and apparatus
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an...
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7581219 |
Transitioning between virtual machine monitor domains in a virtual machine environment
Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related...
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7580040 |
Interruptible GPU and method for processing multiple contexts and runlists
A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed...
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7577952 |
Common state sequences in a finite state machine
A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address...
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7565659 |
Light weight context switching
To alleviate at least some of the costs associated with context switching, addition fields, either with associated Application Program Interfaces (APIs) or coupled to application modules, can be...
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7559063 |
Program flow control in computer systems
Application programs supporting multiple contexts on a computer system having an operating system supporting threads. The method comprises processing a context processing instruction from the...
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7558723 |
Systems and methods for bimodal device virtualization of actual and idealized hardware-based devices
Various embodiments of the present invention are directed to bimodal virtual device approaches (that is, “bimodal devices”). In certain embodiments, the bimodal device is a virtual device that...
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7555607 |
Program thread syncronization for instruction cachelines
In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or...
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7552433 |
Non-platform-specific unique indentifier generation
A method of generating a unique identifier without requiring platform-specific software, a computer readable medium embodying instructions for implementing the method, and a system therefor are...
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7549150 |
Method and system for detecting potential races in multithreaded programs
A dynamic race detection system and method overcomes drawbacks of previous lockset approaches, which may produce many false positives, particularly in the context of thread fork/join and...
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7545381 |
Interruptible GPU and method for context saving and restoring
A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first...
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7539986 |
Method for guest operating system integrity validation
A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first...
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7536690 |
Deferred task swapping in a multithreaded environment
A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has...
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7536541 |
Parallelizing multiple boot images with virtual machines
A system and method are presented for converting a multi-boot computer to a virtual machine. Existing boot images on a multi-boot computer are identified and converted into virtual machine...
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7533207 |
Optimized interrupt delivery in a virtualized environment
Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit...
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7529915 |
Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source
Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch...
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7529854 |
Context-aware systems and methods location-aware systems and methods context-aware vehicles and methods of operating the same and location-aware vehicles and methods of operating the same
Context-aware systems and methods, location-aware systems and methods, context-aware vehicles and methods of operating the same, and location-aware vehicles and methods of operating the same are...
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7526767 |
Methods for automatic group switching according to a resource plan
A resource scheduler is provided for allocating a computer system resource to database management system (DBMS) processes. The resource scheduler operates according to resource plans and resource...
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7526579 |
Configurable input/output interface for an application specific product
A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and...
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7523455 |
Method and system for application managed context switching
A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If...
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7512952 |
Task switching with state preservation for programs running on an electronic device
A method and system providing switching between a plurality of installed programs in a computer system. Embodiments include a jump function comprising the steps: (1) determining a jump program that...
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7512773 |
Context switching using halt sequencing protocol
A halt sequencing protocol permits a context switch to occur in a processing pipeline even before all units of the processing pipeline are idle. The context switch method based on the halt...
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7503049 |
Information processing apparatus operable to switch operating systems
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
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7503048 |
Scheduling synchronization of programs running as streams on multiple processors
Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating...
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7502876 |
Background memory manager that determines if data structures fits in memory with memory state transactions map
A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map...
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7500244 |
Adaptive algorithm for selecting a virtualization algorithm in virtual machine environments
Method for selecting a virtualization algorithm to virtualize a context change. An exit-enter time (EET) to exit and enter a context and a save-restore time (SRT) to save and restore a machine...
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7496921 |
Processing block with integrated light weight multi-threading support
A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various...
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7493621 |
Context switch data prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
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7492718 |
Serial protocol controller that supports subroutine calls
Described is a protocol controller that supports calls to a packet subroutine which includes a packet processing engine programmed to retrieve packets from a packet memory and to interpret the...
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7490223 |
Dynamic resource allocation among master processors that require service from a coprocessor
An apparatus and a method dynamically reassign resources in a coprocessor among master processors that require service from the coprocessor. The method includes each processor, in each processor...
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7487507 |
Secure control transfer in information system
Methods and/or systems and/or apparatus for improved security in information processing systems provide secure control transfer and object-oriented programming support at an architectural level...
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7487319 |
Resource allocation unit queue
Provided is a method, system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends...
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7480706 |
Multi-threaded round-robin receive for fast network port
A method of processing network data in a network processor includes assigning a group of receive threads to process network data from a port. Each of the group of receive threads process network...
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7478394 |
Context-corrupting context switching
A virtual machine application interrupts execution of a host OS under software control at a predetermined interruption point, instead of interrupting the execution at an arbitrary instruction. The...
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7478389 |
Techniques for implementing security on a small footprint device using a context barrier
A small footprint device, such as a smart card, can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context...
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7472393 |
Method and system for real time scheduler
Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to...
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7469321 |
Software process migration between coherency regions without cache purges
A multiprocessor computer system has nodes which use processor state information to determine which coherent caches are required to examine a coherency transaction produced by a single originating...
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7454756 |
Method, apparatus and system for seamlessly sharing devices amongst virtual machines
A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the...
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7454600 |
Method and apparatus for assigning thread priority in a processor or the like
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
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7441245 |
Phasing for a multi-threaded network processor
A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units...
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7434224 |
Plural operating systems having interrupts for all operating systems processed by the highest priority operating system
Multiple different operating systems are enabled to run concurrently on the same computer. A first operating system is selected to have a relatively high priority (the realtime operating system,...
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7434223 |
System and method for allowing a current context to change an event sensitivity of a future context
The present invention provides a system and method, operable in a multi-context processor, for allowing a current context to change an event sensitivity of a future context. In one embodiment, the...
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