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7617496 |
Macroscalar processor architecture
A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed...
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7617495 |
Resource-aware scheduling for compilers
Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when...
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7613599 |
Method and system for virtual prototyping
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
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7590976 |
Compiler program, a computer-readable storage medium storing a compiler program, a compiling method and a compiling unit
The present invention relates a compiler program, a computer-readable storage medium storing such a compiler program, a compiling method and a compiling unit, and an object thereof is to...
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7581215 |
Dependency analysis system and method
We present a technique to perform dependence analysis on more complex array subscripts than the linear form of the enclosing loop indices. For such complex array subscripts, we decouple the...
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7581210 |
Compiler-scheduled CPU functional testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically...
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7565343 |
Search apparatus and search management method for fixed-length data
Fixed-length data ( 560 ) contained in a database ( 560 ) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a...
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7546592 |
System and method for optimized swing modulo scheduling based on identification of constrained resources
A method, computer program product, and a data processing system for scheduling instructions in a data processing system are provided. Dependencies among a plurality of nodes are analyzed to...
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7539884 |
Power-gating instruction scheduling for power leakage reduction
A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing...
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7523449 |
System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture
A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable...
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7516481 |
Program development supporting apparatus, method, program and recording medium
A program development supporting apparatus that groups a plurality of events each executed in an information processor to divide the events into a plurality of parallel execution units to be...
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7509634 |
SIMD instruction sequence generating program, SIMD instruction sequence generating method and apparatus
A translator receives a source code that is described using a process designation (such as a line-by-line process designation, a line data extraction designation, and a broadcast designation) to be...
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7506331 |
Method and apparatus for determining the profitability of expanding unpipelined instructions
A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions...
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7506326 |
Method and apparatus for choosing register classes and/or instruction categories
An improved method, apparatus, and computer instructions for generating instructions to process multiple similar expressions. Parameters are identified for the expressions in the original...
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7493611 |
Pinning internal slack nodes to improve instruction scheduling
A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with...
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7493609 |
Method and apparatus for automatic second-order predictive commoning
A method and apparatus for automatic second-order predictive commoning is provided by the present invention. During an analysis phase, the intermediate representation of a program code is analyzed...
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7487337 |
Back-end renaming in a continual flow processor pipeline
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ...
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7487336 |
Method for register allocation during instruction scheduling
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands.
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7478379 |
Method for minimizing spill in code scheduled by a list scheduler
A technique of ordering machine instructions to reduce spill code. For each machine instruction that is ready for scheduling, an amount is determined by which the size of a committed set of machine...
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7448031 |
Methods and apparatus to compile a software program to manage parallel μcaches
Methods and apparatus to compile a software program to manage parallel μ caches are disclosed. In an example method, a compiler attempts to schedule a software program such that load instructions...
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7447732 |
Recoverable return code tracking and notification for autonomic systems
A system, method and article of manufacture return code management in autonomic systems and more particularly to managing execution of operations in data processing systems on the basis of return...
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7444628 |
Extension of swing modulo scheduling to evenly distribute uniform strongly connected components
A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data...
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7441110 |
Prefetching using future branch path information derived from branch prediction
A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful...
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7434211 |
Transient shared computer resource and settings change bubble for computer programs
Described is a mechanism that preserves the state of computer system shared resources and/or settings, and ensures that changes thereto are reverted when an application exits. A shared resource...
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7415700 |
Runtime quality verification of execution units
One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the...
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7401329 |
Compiling computer programs to exploit parallelism without exceeding available processing resources
A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at...
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7395532 |
Process for running programs on processors and corresponding processor system
Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to...
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7395531 |
Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements
A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized...
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7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis
Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with...
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7386844 |
Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions
A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine...
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7383544 |
Compiler device, method, program and recording medium
Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in...
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7337439 |
Method for increasing the speed of speculative execution
A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate...
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7328433 |
Methods and apparatus for reducing memory latency in a software application
Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce...
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7316012 |
System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops
An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one...
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7308683 |
Ordering of high use program code segments using simulated annealing
An apparatus, program product and method utilize a heuristic-based algorithm such as simulated annealing to order program code segments in a computer memory to provide improved computer performance...
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7308681 |
Control flow based compression of execution traces
A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is...
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7302680 |
Data repacking for memory accesses
A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the...
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7240345 |
Data processing apparatus and associated method
In accordance with a plurality of processing requests, a SAM chip generates IC card entity data including job execution order data showing an order of execution of a plurality of jobs forming...
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7234136 |
Method and apparatus for selecting references for prefetching in an optimizing compiler
One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a...
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7234135 |
Method for processing data using external and internal identifiers to provide reliable access to the data even when reconfigurations of the data occur, and associated system
A method for processing data in a data processing system ( 1 ) which includes a number of data processing units ( 2 ), and operator and observation units ( 4 ), which are interconnected by way of a...
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7213244 |
Apparatus and method for distribution of work on a doubly linked list among processing threads
An apparatus and method for distributing work on a doubly linked list to a plurality of worker threads are provided. With the apparatus and method, an initial thread obtains the list lock for the...
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7185327 |
System and method for optimizing operations via dataflow analysis
A method for modifying serial dependencies in a procedure includes a step of building a graph representation of the procedure. The graph representation has an origin as well as a unique position,...
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7181730 |
Methods and apparatus for indirect VLIW memory allocation
Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of...
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7140010 |
Method and apparatus for simultaneous optimization of code targeting multiple machines
Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the...
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7114151 |
Code conversion method and apparatus
Interlocked floating-point instructions are detected, and a register address referring to and assigning an operand in the interlocked instructions is changed to an odd-number address not assigned...
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7107291 |
Information system and data access method
A data access method in an information system including a plurality of data utilization systems connected to a network N 1 , and a plurality of data provision systems connected to a network,...
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7103882 |
Optimization apparatus, complier program, optimization method and recording medium
An optimization apparatus (compiler program, method and recording medium) for changing the order of execution of instructions in a program to be optimized includes an exception occasion instruction...
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7100157 |
Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor
Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor are disclosed. In an example, a compiler inserts decision code into the object code to thereby cause...
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7089545 |
Detection of reduction variables in an assignment statement
This invention relates to a method, system and program product to detect reduction variables in assignment statements in the source code for enabling the parallel execution of program loops. The...
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7082602 |
Function unit based finite state automata data structure, transitions and methods for making the same
We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit...
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