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7082602 |
Function unit based finite state automata data structure, transitions and methods for making the same
We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit...
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7080367 |
Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor
When a branch instruction is decoded by the instruction decoders 409 a ˜409 c , the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator ...
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7076777 |
Run-time parallelization of loops in computer programs with static irregular memory access patterns
Run-time parallelization of loops with static irregular read-write memory access patterns is performed across multiple arrays. More than one element from each array can be read or written during...
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7073169 |
Compiler device with branch instruction inserting unit
A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a...
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7069189 |
Method and apparatus for controlling multiple resources using thermal related parameters
In some embodiments of the present invention, a method and system are provided in a multiple resource environment for relieving a thermal condition by applying cooling techniques or throttling to...
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7058938 |
Method and system for scheduling software pipelined loops
A method and a system for scheduling a software pipelined loop with indirect loads. The system may include a data structure in communication with a processor and a memory. The processor may...
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7058937 |
Methods and systems for integrated scheduling and resource management for a compiler
A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function...
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7055144 |
Method and system for optimizing the use of processors when compiling a program
A method and system for optimizing the use of a plurality of processors when compiling a program in a computer system is disclosed. The method and system comprises providing a list of directories...
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7028290 |
Method and apparatus for prioritizing software tests
A computer system and method is provided for prioritizing software tests. Software tests are prioritized based on coverage indicators for the software tests and an indication of impacted areas of...
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7013460 |
Specifying an invariant property (range of addresses) in the annotation in source code of the computer program
Method and apparatus for verifying at runtime an invariant property of a data structure. In various example embodiments, code that verifies whether a runtime value of the data structure is...
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6993757 |
Method and apparatus for multi-versioning loops to facilitate modulo scheduling
One embodiment of the present invention provides a system that facilitates multi-versioning loops to facilitate modulo scheduling. Upon receiving a computer program, the system analyzes the code to...
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6988266 |
Method of transforming variable loops into constant loops
A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable...
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6976157 |
Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables
Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of...
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6952817 |
Generating hardware interfaces for designs specified in a high level language
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to...
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6938247 |
Small memory footprint system and method for separating applications within a single virtual machine
A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is...
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6922826 |
Debugger impact reduction through breakpoint motion
A first type of debugger impact reduction includes removing, from within a loop, an initial conditional breakpoint (“ICB”); extracting a first Boolean expression (“BE_1”) therefrom; setting...
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6922824 |
System and method for transforming object code
A method comprising: converting bytecodes into a graph of jop objects to track where jump operations pointed before modification of the bytecodes; adjusting constant pool references from local to...
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6918111 |
System and method for scheduling instructions to maximize outstanding prefetches and loads
The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue...
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6912640 |
Method to partition large code across multiple e-caches
A method for executing an instruction stream includes partitioning the instruction stream using a partition point to obtain a first partition of the instruction stream and a second partition of the...
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6912709 |
Mechanism to avoid explicit prologs in software pipelined do-while loops
The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a...
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6901586 |
Safe language static variables initialization in a multitasking system
A system and method are provided for thread-safe initialization of static variables in a multitasking system. In one embodiment, the static fields of a class may be “virtualized” such that each...
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6895580 |
Expression reduction during compilation through routine cloning
An apparatus, program product, and method utilize routine cloning to optimize the performance of a compiled computer program. Within a compiled representation of a computer program, an...
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6883166 |
Method and apparatus for performing correctness checks opportunistically
A method and an apparatus that enable spare instruction slots within a code module to be utilized opportunistically for insertion of instructions associated with correctness check functions. The...
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6880074 |
In-line code suppression
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes)...
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6871343 |
Central processing apparatus and a compile method
Systems and methods are disclosed for generating a program executed by a central processing apparatus for assigning instructions of the program. The systems and methods may include dividing the...
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6836882 |
Pipeline flattener for simplifying event detection during data processor debug operations
Pipeline activity information associated with all stages of execution of an instruction in an instruction pipeline of a data processor is presented to an event detector in timewise aligned format....
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6832370 |
Data speculation within modulo scheduled loops
Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for...
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6772415 |
Loop optimization with mapping code on an architecture
A loop transformation step, to be performed on code and improving data transfer and storage, while executing said transformed code on a parallel processor, is disclosed. Improval of the data...
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6757892 |
Method for determining an optimal partitioning of data among several memories
A method and system for optimizing variable locations within disparate storage elements in a target processing environment according to a least cost analysis based upon the number of times a...
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6754893 |
Method for collapsing the prolog and epilog of software pipelined loops
A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes...
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6751792 |
Using value-expression graphs for data-flow optimizations
A new method and apparatus for use in post compilation optimizers is presented. The present invention is based on the use of a new graphical representation of code in a linked program called an...
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6748590 |
Method for generating instruction sequences for integer multiplication
The invention pertains to an improved method for generating ALU instruction sequences for performing integer multiplication. The invention analytically helps to find an optimal sequence of shift,...
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6738893 |
Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations
A process for scheduling computer processor execution of operations in a plurality of instruction word formats including the steps of arranging commands into properly formatted instruction words...
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6718541 |
Register economy heuristic for a cycle driven multiple issue instruction scheduler
A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a...
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6675380 |
Path speculating instruction scheduler
Path speculating instruction scheduler. According to one embodiment of the present invention instructions are placed into a control flow graph having blocks of the instructions, the control flow...
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6671878 |
Modulo scheduling via binary search for minimum acceptable initiation interval method and apparatus
Disclosed herein is an instruction set scheduling system for scheduling instruction sets in a pipelined processing system. In particular, the scheduling system includes a binary search technique...
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6658551 |
Method and apparatus for identifying splittable packets in a multithreaded VLIW processor
A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional...
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6654952 |
Region based optimizations using data dependence graphs
Region based optimization may be accomplished by creating dependence graphs for each block and then incrementally computing a single dependence graph for the region. First dependence DAGs are...
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6651247 |
Method, apparatus, and product for optimizing compiler with rotating register assignment to modulo scheduled code in SSA form
In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first...
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6637026 |
Instruction reducing predicate copy
When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same...
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6634023 |
Compile method, exception handling method and computer
The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is...
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6634024 |
Integration of data prefetching and modulo scheduling using postpass prefetch insertion
The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce...
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6615403 |
Compare speculation in software-pipelined loops
The present invention provides a mechanism for implementing compare speculation in software pipelined loops. A data dependency graph (DDG) is generated for a loop that includes a control compare...
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6609248 |
Cross module representation of heterogeneous programs
An output translator provides for cross module representations of components within a heterogeneous program by translating modifying a platform-neutral intermediate representation (IR) of the...
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6609249 |
Determining maximum number of live registers by recording relevant events of the execution of a computer program
The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the...
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6588009 |
Method and apparatus for compiling source code using symbolic execution
A method and apparatus for optimizing the compilation of a computer program by exposing parallelism are disclosed. Information describing the operations in the program and their sequence is...
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6567976 |
Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code
A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of “unroll and jam” on selected loop nests. The present...
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6526573 |
Critical path optimization-optimizing branch operation insertion
A compiler optimization method for optimizing a scheduled block of instructions inserts a conditional branch instruction in place of a merge instruction to select between alternative paths when a...
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6516462 |
Cache miss saving for speculation load operation
Compiler optimization methods and systems for preventing delays associated with a speculative load operation on a data when the data is not in the data cache of a processor. A compiler optimizer...
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6507947 |
Programmatic synthesis of processor element arrays
A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified...
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