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9038044 Code patching for non-volatile memory  
Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a...
9021454 Operand and limits optimization for binary translation system  
Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for...
9015685 Code analysis for simulation efficiency improvement  
A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application...
9003384 Methods and apparatuses for automatic type checking via poisoned pointers  
A method and an apparatus that modify pointer values pointing to typed data with type information are described. The type information can be automatically checked against the typed data leveraging...
8997073 Semi-automatic restructuring of offloadable tasks for accelerators  
A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and...
8990791 Intraprocedural privatization for shared array references within partitioned global address space (PGAS) languages  
Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that...
8990786 Program optimizing apparatus, program optimizing method, and program optimizing article of manufacture  
An apparatus having a transactional memory enabling exclusive control to execute a transaction. The apparatus includes: a first code generating unit configured to interpret a program, and generate...
8972958 Multistage development workflow for generating a custom instruction set reconfigurable processor  
Systems and systems which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the...
8972704 Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory  
A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by...
8972959 Method of converting program code of program running in multi-thread to program code causing less lock collisions, computer program and computer system for the same  
A method of converting a program code of a program running in multi-thread to a program code which causes fewer lock collisions. The method includes reading the program code into a memory and...
8972961 Instruction scheduling approach to improve processor performance  
A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization...
8966459 Processors and compiling methods for processors  
A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a...
8966461 Vector width-aware synchronization-elision for vector processors  
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent...
8949809 Automatic pipeline parallelization of sequential code  
A system and associated method for automatically pipeline parallelizing a nested loop in sequential code over a predefined number of threads. Pursuant to task dependencies of the nested loop, each...
8943486 Multiple instruction execution mode resource-constrained device  
A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the...
8943600 Weighted security analysis  
A method, computer program product, and system for transforming unit tests is described. A unit test associated with one or more software units is identified. A graphical representation of a...
8935685 Instruction scheduling approach to improve processor performance  
A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization...
8935795 Weighted security analysis  
A method, computer program product, and system for transforming unit tests is described. A unit test associated with one or more software units is identified. A graphical representation of a...
8935683 Inline function linking  
In general, techniques are described for performing a form of inline dead code elimination. An apparatus comprising a storage unit and a processor may implement these techniques. The storage unit...
8930928 Method for modifying the assembly output of a compiler  
The present invention performs manipulations on the assembly file level. As a compiler outputs an assembly file, the assembly file may be inspected and modified before it is sent to the assembler....
8930935 Composite service refactoring  
A network device may include a memory to store instructions. The network device may further include a processor to execute the instructions to obtain information relating to a loosely-coupled...
8918772 Statically analyzing program correctness for a dynamic programming language  
One embodiment of the present invention provides a system that uses static analysis to determine program correctness for a program written in a dynamic programming language. During operation, the...
8910135 Structure layout optimizations  
More effective compiler optimizations provide improved cache utilization. The compiler optimizations include a structure layout optimization that leaves the physical layout of the structure fields...
RE45278 Method and apparatus for changing microcode to be executed in a processor  
A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control...
8904372 Dialog to service conversion method and system  
A computer implemented system and method includes accessing an application dialog from a computer readable storage device, wherein the application dialog contains process modules having interface...
8904369 Method and system for automated process distribution  
A method for automated process distribution includes selecting a process definition; identifying a first process portion and at least one second process portion in the process definition;...
8898648 Methodology for fast detection of false sharing in threaded scientific codes  
A profiling tool identifies a code region with a false sharing potential. A static analysis tool classifies variables and arrays in the identified code region. A mapping detection library...
8893103 Automatic asynchronous offload to many-core coprocessors  
Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a...
8887142 Loop control flow diversion  
Loop control flow diversion supports thread synchronization, garbage collection, and other situations involving suspension of long-running loops. Divertible loops have a loop body, a loop top, an...
8875115 Type merging technique to reduce class loading during Java verification  
An apparatus, process, and computer program product to merge types in an object-oriented program is disclosed herein. In one embodiment, a process may include analyzing a method within an...
8869109 Disassembling an executable binary  
A method for disassembling an executable binary (binary). In one implementation, a plurality of potential address references may be identified based on the binary and a plurality of storage...
8863079 Efficient and expansive conversions between reference and primitive  
A tool, such as a compiler or an interpreter, receives program source code and determines that the code includes an operation for which type conversion is permitted on an operand. The tool...
8863132 Using abstraction layers to facilitate communication between systems  
Systems and methods are provided for enabling communication between two systems using different commands, variables, protocols, methods, or instructions. In an embodiment, exit points in a software...
8850574 Safe self-modifying code  
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for runtime language-independent sandboxing of software. In one aspect, a system implements an...
8850410 System using a unique marker with each software code-block  
A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of...
8832672 Ensuring register availability for dynamic binary optimization  
A compiler compiles code in a target program by reserving at least one register for use by a dynamic binary optimizer during target program execution. When the target program is subsequently...
8826255 Restructuring control flow graphs generated from a model  
A control flow graph may be generated from a model. The control flow graph may be restructured by converting at least one cyclical unstructured region of a control flow graph into a structured...
8826257 Memory disambiguation hardware to support software binary translation  
A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of...
8813041 Efficient compression of applications  
In one embodiment, a method for inserting advertising into an application includes removing first application code from a first input executable file and placing it into an output executable file,...
8813044 Dynamic optimization of mobile services  
A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service. This service process definition is comprised of computer readable...
8813057 Branch pruning in architectures with speculation support  
According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The...
8806465 Refactor exception class hierarchy for reduced footprint and faster application start  
A method, system, and program product for removing exception classes that match a pattern is disclosed. Exception classes are searched for those of the exception classes that match that pattern....
8799448 Generating rule packs for monitoring computer systems  
Improved systems and methods for developing rule packs can include receiving monitoring rules specified in a markup language, and combining them to produce a rule pack. Combining processes can...
8793675 Loop parallelization based on loop splitting or index array  
Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are...
8789029 Optimizing program by reusing execution result of subclass test function  
A technique for optimizing a program by reusing an execution result of a subclass test function. It includes a reusability determining unit to determine reusability of code of a subclass test...
8789025 Path-sensitive analysis for reducing rollback overheads  
A mechanism is provided for path-sensitive analysis for reducing rollback overheads. The mechanism receives, in a compiler, program code to be compiled to form compiled code. The mechanism divides...
8782625 Memory safety of floating-point computations  
Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any...
8769513 Latency hiding of traces using block coloring  
An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information....
8769507 Dynamic optimization of mobile services  
A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service on a specified computing device. This service process definition is...
8769515 Semantic intensity based decomposition of software systems  
A computer-implemented technique for analysis of software, is carried out using a semantic intensity calculation module, a coupling calculation module, and a software decomposition module. Software...