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7620922 |
Method and system for optimized circuit autorouting
An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit...
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7614028 |
Representation, configuration, and reconfiguration of routing method and system
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of...
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7614025 |
Method of placement for iterative implementation flows
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7610568 |
Methods and apparatus for making placement sensitive logic modifications
Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already...
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7607113 |
Wiring pattern determination method and computer program product thereof
A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions...
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7607112 |
Method and apparatus for performing metalization in an integrated circuit process
A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that...
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7603643 |
Method and system for conducting design explorations of an integrated circuit
Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that...
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7603640 |
Multilevel IC floorplanner
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions...
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7596773 |
Automating optimal placement of macro-blocks in the design of an integrated circuit
Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of optimalness for each placement is computed....
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7594212 |
Automatic pin placement for integrated circuits to aid circuit board design
A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus...
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7594205 |
Interface configurable for use with target/initiator signals
Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of...
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7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
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7590962 |
Design method and architecture for power gate switch placement
A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
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7587699 |
Automated system for designing and developing field programmable gate arrays
An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is...
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7587696 |
Semiconductor device, layout method and apparatus and program
A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is...
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7587695 |
Protection boundaries in a parallel printed circuit board design environment
Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of...
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7584445 |
Sequence-pair creating apparatus and sequence-pair creating method
A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block b i in a block set B and information of block placement, creates a...
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7581201 |
System and method for sign-off timing closure of a VLSI chip
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7577933 |
Timing driven pin assignment
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design...
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7571415 |
Layout of power device
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The...
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7571410 |
Resonant tree driven clock distribution grid
An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein....
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7571409 |
Circuit design device and circuit design program
A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library...
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7571408 |
Methods and apparatus for diagonal route shielding
An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may...
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7568177 |
System and method for power gating of an integrated circuit
Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is...
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7565638 |
Density-based layer filler for integrated circuit design
A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may...
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7565637 |
Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same
A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin...
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7562327 |
Mask layout design improvement in gate width direction
In a cell comprising an N well and a P well, a distance SP 04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to...
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7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate
A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the...
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RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry
An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer...
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7555734 |
Processing constraints in computer-aided design for integrated circuits
A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow...
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7539966 |
Enhanced OP3 algorithms for net cuts, net joins, and probe points for a digital design
Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a...
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7539964 |
Cell placement taking into account consumed current amount
A computer-readable record medium having a program embodied therein for causing a computer to place cells. The program includes codes for causing the computer to perform deriving an amount of...
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7536666 |
Integrated circuit and method of routing a clock signal in an integrated circuit
The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data...
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7536664 |
Physical design system and method
A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and...
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7536661 |
Incremental placement during physical synthesis
A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The...
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7536659 |
Semiconductor memory device and semiconductor device
Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other...
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7536658 |
Power pad synthesizer for an integrated circuit design
A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two...
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7533363 |
System for integrated circuit layout partition and extraction for independent layout processing
A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide...
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7533358 |
Integrated sizing, layout, and extractor tool for circuit design
Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of...
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7523430 |
Programmable logic device design tool with simultaneous switching noise awareness
A logic design system is provided for designing programmable logic device integrated circuits with minimized simultaneous switching noise. The logic design system identifies input-output drivers...
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7523429 |
System for designing integrated circuits with enhanced manufacturability
A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout...
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7523419 |
Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus method thereof, and maunfacturing apparatus thereof
Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 ...
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7519943 |
Photomask fabrication method
The simulation method is for simulating a pattern to be transferred onto a photoresist film by exposure using a photomask with a main pattern 10 and an assist pattern 12 formed on. The...
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7519933 |
Converging repeater methodology for channel-limited SOC microprocessors
A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the...
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