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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7614025 |
Method of placement for iterative implementation flows
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7607112 |
Method and apparatus for performing metalization in an integrated circuit process
A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that...
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7603643 |
Method and system for conducting design explorations of an integrated circuit
Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that...
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7603641 |
Power/ground wire routing correction and optimization
A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a...
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7603640 |
Multilevel IC floorplanner
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions...
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7603637 |
Secure, stable on chip silicon identification
A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a...
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7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
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7594206 |
Fault detecting method and layout method for semiconductor integrated circuit
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
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7594205 |
Interface configurable for use with target/initiator signals
Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of...
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7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
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7590962 |
Design method and architecture for power gate switch placement
A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
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7587695 |
Protection boundaries in a parallel printed circuit board design environment
Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of...
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7581202 |
Method for generation, placement, and routing of test structures in test chips
A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7577931 |
Semiconductor device and method of manufacturing the same
A semiconductor device has power supply pads including a first power supply pad and at least one second power supply pad that are connected to internal power supply wirings through an internal...
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7571410 |
Resonant tree driven clock distribution grid
An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein....
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7571408 |
Methods and apparatus for diagonal route shielding
An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may...
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7568176 |
Method, system, and computer program product for hierarchical integrated circuit repartitioning
A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more...
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7565637 |
Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same
A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin...
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7562327 |
Mask layout design improvement in gate width direction
In a cell comprising an N well and a P well, a distance SP 04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to...
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7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate
A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the...
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7562316 |
Apparatus for power consumption reduction
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block...
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RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry
An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer...
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7555733 |
Hierarchical partitioning
Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several...
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7546559 |
Method of optimization of clock gating in integrated circuit designs
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for...
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7543259 |
Method and device for deciding support portion position in a backup device
A host computer 80 for wholly controlling an electronic component mounting line displays a surface side image and a reverse side image which respectively show a surface side and a reverse side of...
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7543249 |
Embedded switchable power ring
An integrated circuit comprises an embedded switchable power ring for supplying power to circuit modules ( 15.1, . . . , 15.5 ) arranged within the switchable power ring ( 13 ). The switchable...
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7539964 |
Cell placement taking into account consumed current amount
A computer-readable record medium having a program embodied therein for causing a computer to place cells. The program includes codes for causing the computer to perform deriving an amount of...
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7539962 |
Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device
There is provided a method of correcting pattern data for a semiconductor device, including acquiring pattern data for a lower layer, pattern data for an upper layer, and pattern data for a...
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7539961 |
Library-based solver for modeling an integrated circuit
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for...
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7539893 |
Systems and methods for speed binning of integrated circuits
Methods and apparatus sort integrated circuits by maximum operating speed (f max ). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for...
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7536661 |
Incremental placement during physical synthesis
A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The...
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7536658 |
Power pad synthesizer for an integrated circuit design
A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two...
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7533363 |
System for integrated circuit layout partition and extraction for independent layout processing
A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide...
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7533357 |
Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis
A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution...
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7530045 |
Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlines
A method of placing a circuit design on a target device can include subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition...
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7526739 |
Methods and systems for computer aided design of 3D integrated circuits
Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a...
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7524685 |
Manufacturing method of a display device
The present invention provides a manufacturing method of a display device which can decrease the lowering of a yield rate of the display device attributed to the aggregations generated by pseudo...
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7523419 |
Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus method thereof, and maunfacturing apparatus thereof
Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 ...
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7516434 |
Layout design program, layout design device and layout design method for semiconductor integrated circuit
A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to...
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7512921 |
Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors
A layout method in a layout apparatus for layout of an integrated circuit includes placing a plurality of cells at approximate positions according to the circuit data and placing the plurality of...
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7509622 |
Dummy filling technique for improved planarization of chip surface topography
The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while...
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7509547 |
System and method for testing of interconnects in a programmable logic device
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
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7509247 |
Electromagnetic solutions for full-chip analysis
A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may...
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7502721 |
Product design support system, product design support method, and program
A product design support system comprises a product design support server ( 1 ), a product design support database ( 2 ) where parts information, parts image information, circuit information and...
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