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6813756 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program  
With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with...
6804809 System and method for defining a semiconductor device layout  
A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating...
6802050 Efficient layout strategy for automated design layout tools  
A method is described that involves automatically laying out a circuit structure in software by describing in a software environment the placement of a gate structure relative to a diffusion...
6802043 Semiconductor device having a function block provided in a macro and operating independently of the macro and method for designing the same  
A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function...
6802047 Calculating resistance of conductor layer for integrated circuit design  
A variational method is used for calculating resistance of a conductor layer for an integrated circuit design, the conductor layer having a geometric shape defined by boundary edges. The method...
6799313 Space classification for resolution enhancement techniques  
The present invention comprises a method and apparatus for classifying edges for implementing mask corrections. In one embodiment, classifications are based upon proximity ranges bounded on one...
6799304 Arbitration within a multiport AMBA slave  
A circuit generally comprising an interface circuit and an arbitration circuit is disclosed. The interface circuit may be couplable between a peripheral device and a plurality of ports. The...
6799310 Integrated circuit layout method and program for mitigating effect due to voltage drop of power supply wiring  
An integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells (or function macros) that are to be laid out in order of...
6799309 Method for optimizing a VLSI floor planner using a path based hyper-edge representation  
An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level...
6795957 Method of designing power vias in an IC layout  
An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree keeping track of power wires and other objects within...
6795956 Semiconductor device, and method and program for designing the same  
A semiconductor device is designed by disposing a plurality of cells. The semiconductor device is equipped with a semiconductor substrate 1 , transistors formed in the semiconductor substrate, a...
6792584 System and method for designing an integrated circuit  
The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and...
6792585 Method and apparatus of relative datapath cell placement with structure bonding  
The invention discloses a relative structure placement of datapath of cell instances in a column structure, a row structure, or an array structure. To encourage placement of a desirable structure,...
6792586 Correction of spacing violations between wide class objects of dummy geometries  
Automated techniques to correct certain rule violations with respect to non-design geometries are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a...
6789245 Use of coupling capacitance to balance skew in a network  
Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is...
6789246 Method and apparatus for automatic layout of circuit structures  
A method is described that involves retrieving a generic layout description of a circuit structure from a first database that stores a plurality of generic layout descriptions. The method also...
6789244 Placement of clock objects under constraints  
Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an...
6789243 Interactive floor planner apparatus for circuit blocks  
The present invention relates to an interactive floor planner apparatus for determining a placement position of functional blocks, in which apparatus functional block information including...
6785871 Automatic recognition of an optically periodic structure in an integrated circuit design  
A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit...
6785875 Methods and apparatus for facilitating physical synthesis of an integrated circuit design  
Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is...
6782522 Semiconductor device having wide wiring pattern in outermost circuit  
A semiconductor electronic part, having a lot of bumps allocated in a checkered pattern, is solder-mounted on a multilayer circuit board. In the multilayer circuit board, a first wiring pattern...
6778999 Method for distributing a set of objects in computer application  
A method of determining redistribution of objects among three or more containers in a network comprises determining an initial set of objects in each of the containers, identifying neighboring...
6779163 Voltage island design planning  
A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage...
6779164 LSI design method having dummy pattern generation process and LCR extraction process and computer program therefor  
In the present invention, conductive dummy patterns continuous in a direction perpendicular to adjacent wiring patterns are inserted at a first distance from the adjacent wiring patterns between...
6775812 Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit  
An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape....
6775813 Aggregation of storage elements into stations and placement of same into an integrated circuit or design  
The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within...
6775811 Chip design method for designing integrated circuit chips with embedded memories  
A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in...
6772401 Correction of spacing violations between design geometries and wide class objects of dummy geometries  
Automated techniques to correct certain rule violations with respect to non-design geometries are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a...
6769097 Scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics  
The present invention is directed to a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics. A method for allocating resources in a design of an integrated...
6769105 Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits  
The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented...
6766501 System and method for high-level test planning for layout  
A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of...
6763506 Method of optimizing the design of electronic systems having multiple timing constraints  
An electronic representation of the electronic design is received which includes various connections between various blocks specifying functions performed within the electronic design. Each of the...
6763509 Method and apparatus for allocating decoupling capacitor cells  
A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in the IC design, each of the...
6760896 Process layout of buffer modules in integrated circuits  
A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined...
6760899 Dedicated resource placement enhancement  
Method and code for dedicated resource placement enhancement is described. More particularly, a local area of a network is obtained for determining placement options of logic blocks to increase...
6757880 Logical circuit designing device, logical circuit designing method, storage medium and program  
By comprising a logical circuit storage unit for storing a logical circuit, a transmission line circuit generation unit for generating a transmission line circuit based on the logical circuit...
6757883 Estimating free space in IC chips  
Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons...
6757885 Length matrix generator for register transfer level code  
A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a...
6754549 Parts mounting apparatus and parts checking method by the same  
The present invention allows a parts remaining number to be efficiently controlled using adaptability check result of an electronic part added during operation, and allows the electronic part to be...
6754880 Method for automatically laying out semiconductor integrated circuit  
The present invention is directed to a semiconductor integrated circuit automatic lay-out method using a cell group constituted of a core cell in which a transistor and/or a logic gate are arranged...
6754879 Method and apparatus for providing modularity to a behavioral description of a circuit design  
A method and apparatus for selectively providing modularity and/or hierarchy to a behavioral description of a circuit design. This is accomplished by providing a template call in the behavioral...
6751784 Implementation of networks using parallel and series elements  
The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements....
6748574 Method of and apparatus for determining an optimal solution to a uniform-density layout problem, and medium on which a program for determining the solution is stored  
A uniform-density layout problem requires an optimal layout of multiple elements in a predetermined region under a set of conditions including a density-uniformization condition. The method...
6742165 System, method and computer program product for web-based integrated circuit design  
A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a...
6742170 Repeatable swizzling patterns for capacitive and inductive noise cancellation  
Disclosed herein are swizzling techniques that may provide capacitive and inductive noise cancellation on a set of signal lines. Positive noise due to a capacitive coupling between attacker signal...
6742169 Semiconductor device  
In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are...
6735753 Method of fabricating a semiconductor device having a multilevel interconnections  
In a method of fabricating a semiconductor device, first metal interconnection patterns, first via patterns and second metal interconnection patterns are positioned in such a way that each of...
6735742 Method for optimizing a cell layout using parameterizable cells and cell configuration data  
A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with parameterizable dimensions, calculating a...
6735754 Method and apparatus to facilitate global routing for an integrated circuit layout  
A system that facilitates generating a global routing for a layout of an integrated circuit operates by receiving a netlist to be routed. The system partitions this netlist into global signals,...
6732343 System and methods for placing clock buffers in a datapath stack  
A clock buffer placement system and method are provided for the placement of clock buffers in a datapath stack. In accordance with one aspect of the invention, the system positions at least one...
Matches 401 - 450 out of 939 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >