Matches 351 - 400 out of 937 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6915496 Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique  
An apparatus and method for incorporating driver sizing into buffer insertion such that the two optimization techniques are performed simultaneously are provided. The apparatus and method extends...
6912699 Testing design for flip chip connection process  
A testing design for flip chip connection process. In one embodiment the testing design has a substrate, a plurality of connections formed on said substrate, at least one integrated device and a...
6912487 Utility station automated design system and method  
A system and method provide a computer-based automated tool for quickly and efficiently designing utility stations. One example of such a utility station is a unit substation. The tool includes a...
6912705 Method and apparatus for performing operation on physical design data  
A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC...
6912703 Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation  
A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the...
6910200 Method and apparatus for associating selected circuit instances and for performing a group operation thereon  
A method and apparatus for associating selected circuit instances, and for allowing a later group manipulation thereof. Prior to entering a database editor tool, selected instances may be...
6910202 Logic synthesis device and logic synthesis method  
An analysis part analyzes a description of a logic design; an extraction part extracts a part of the description of the logic design having a fan-out number beyond a predetermined value, based on...
6907583 Computer aided method of circuit extraction  
A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a...
6904571 Algorithm and methodology for the polygonalization of sparse circuit schematics  
An method of creating a physical layout of an integrated circuit. A schematic file ( 600 ) is mapped directly to a physical layout using the location of elements and routing of interconnections as...
6904582 Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same  
A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned...
6898580 Single board computer quotation and design system and method  
The present invention is a virtual product designer that allows a user to provide specifications for a custom board level product and receive an instantaneous cost quotation and feasibility...
6898769 Decoupling capacitor sizing and placement  
A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a...
6895567 Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs  
The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment,...
6895568 Correction of spacing violations between pure fill via areas in a multi-wide object class design layout  
In a Pure Fill Via Area (PFVA) extraction design flow, the extracted PFVAs may violate the minimum via spacing rule with the existing vias and may also violate the minimum via spacing rule among...
6895524 Circuit reduction technique for improving clock net analysis performance  
A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear...
6892367 Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout  
A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the...
6889370 Method and apparatus for selecting and aligning cells using a placement tool  
Methods and apparatus for efficiently identifying, selecting and aligning cells within a circuit design are disclosed. Preferably, a net or group-of nets is first identified by the circuit...
6883149 Via enclosure rule check in a multi-wide object class design layout  
In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries...
6883155 Macro design techniques to accommodate chip level wiring and circuit placement across the macro  
Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may...
6883154 LP method and apparatus for identifying route propagations  
Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a...
6880134 Method for improving capacitor noise and mismatch constraints in a semiconductor device  
In one embodiment, a method ( 50 ) is provided for improving switched capacitor performance by lowering a mismatch constraint to be equal to, or nearly equal to, a noise constraint. The mismatch...
6880143 Method for eliminating via blocking in an IC design  
An IC design indicating positions of cells within an IC is processed to determine whether conductors residing above the cells block via access to an input/output (I/O) terminal on an upper surface...
6876961 Electronic system modeling using actual and approximated system properties  
A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e.g., timing operation) upon both actual physical...
6877144 System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit  
A system and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit are disclosed. The method includes analyzing a pattern in a mask layout...
6874137 Design data processing method and recording medium  
A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b)...
6870255 Integrated circuit wiring architectures to support independent designs  
An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections,...
6865721 Optimization of the top level in abutted-pin hierarchical physical design  
An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and...
6858928 Multi-directional wiring on a single metal layer  
An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections,...
6857107 LSI layout method and apparatus for cell arrangement in which timing is prioritized  
In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing...
6854093 Facilitating press operation in abutted-pin hierarchical physical design  
An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and...
6849947 Semiconductor device and pattern layout method thereof  
The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode...
6851100 Management system for automated wire bonding process  
An integrated management system is provided for automatically executing a procedure of reviewing and editing an assembly reference and a bonding specification used for manufacturing IC packages....
6848092 Layout of networks using parallel and series elements  
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network...
6848091 Partitioning placement method and apparatus  
Some embodiments of the invention are placers that use lines that are not orthogonal with each other to calculate the costs of potential placement configurations. Some of these embodiments use...
6842885 Computer program product for defining slits in a bus on a chip  
A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a...
6842887 Data processing system for designing a layout of an integrated electronic circuit having a multiplicity of electronic components and method of designing a layout  
A data processing system includes a data memory, in which data are stored, the data representing a set of predetermined geometrical basic forms and a set of geometrical operations that can be...
6842886 Basic cell of gate array semiconductor device, gate array semiconductor device, and layout method for gate array semiconductor device  
A basic cell of a gate array semiconductor device, including first and second p-channel MOS transistors and first and second n-channel MOS transistors, wherein the first p-channel MOS transistor...
6832180 Method for reducing noise in integrated circuit layouts  
A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a...
6829749 Design support apparatus for circuit including directional coupler, design support tool, method of designing circuit, and circuit board  
The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit...
6829750 Pass-transistor very large scale integration  
Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by...
6823498 Masterless building block binding to partitions  
A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first...
6823502 Placement of configurable input/output buffer structures during design of integrated circuits  
A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks...
6820241 Semiconductor device with voltage down circuit changing power supply voltage to operating voltage  
A plurality of core chips are arranged on a body of a semiconductor device, and a plurality of voltage down circuits are arranged on the outside of the core chips to lower a power supply voltage to...
6820046 System for electrically modeling an electronic structure and method of operation  
According to the electrical modeling system and method provided by the present invention, the electronic structure to be modeled is segmented into an ordered sequence of segments, each segment is...
6817004 Net segment analyzer for chip CAD layout  
A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting...
6817005 Modular design method and system for programmable logic devices  
In modular design flow, logic designers are able to partition a top-level logic design for a PLD into modules and implement any module independently from other modules. Modules are mapped, placed,...
6815621 Chip scale package, printed circuit board, and method of designing a printed circuit board  
A chip scale package has first and second sets of external signal terminals arranged in rows and columns at respective sides of the bottom surface of the package The spacing between the rows of the...
6813723 Method of compensating for delay between clock signals  
Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of (1)...
6813756 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program  
With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with...
6804809 System and method for defining a semiconductor device layout  
A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating...
Matches 351 - 400 out of 937 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >